Altera SDI II MegaCore - Manual (Page 27)

Figure 3-2: Design Example Entity and Simulation Testbench
Loopback
Path
Ch0
Loopback
(SDI Duplex)
Reconfiguration
Management/Router
Ch1 Test
(SDI RX)
Ch1 DUT
(SDI TX)
Transceiver
Reconfiguration
Controller
Video Pattern
Generator
TX
Checker
RX
Checker
Test
Control
Data
Control
SDI II IP Core
Design Example
Testbench
3-12 Design Examples for Arria V, Cyclone V, and Stratix V Devices
UG-01125
2015.05.04
Altera Corporation SDI II IP Core Getting Started
Send Feedback