Protocol, Transmitter, Protocol -2 – Altera SDI II MegaCore User Manual
Page 44: Transmitter -2
Figure 4-2: SDI II IP Core Block Diagram for Arria 10 Devices
SDI II IP Core for Arria 10
Parallel Video In
Parallel Video Out
SDI Out
SDI In
Protocol
PHY Reset
Controller
TX PLL
Arria 10
Native PHY IP
Protocol
The protocol block handles the SDI-specific parts of the core and generally operates on a parallel domain
data.
Transmitter
The transmitter performs the following functions:
• HD-SDI LN insertion
• Sync bit insertion
• HD-SDI CRC generation and insertion
• Payload ID insertion
• Matching timing reference signal (TRS) word
• Clock enable signal generation
• Scrambling and non-return-zero inverted (NRZI) coding
The block diagrams below illustrate the SDI II IP core transmitter (simplex) data path for each supported
video standard.
For more information about the function of each submodules, refer to the Submodules section.
4-2
Protocol
UG-01125
2015.05.04
Altera Corporation
SDI II IP Core Functional Description