Altera SDI II MegaCore - Manual (Page 18)

Parameterizing the IP Core
To parameterize your IP core, follow these steps:
1. Select the video standard.
2. Select Bidirectional, Transmitter, or Receiver interface direction.
3. Select Combined Transceiver and Protocol, Separate Transceiver or Separate Protocol, (for Arria V,
Cyclone V, and Stratix V devices only).
4. Turn on the necessary transceiver options, (for Arria V, Cyclone V, and Stratix V devices only).
5. Turn on the necessary receiver options.
Some options may be grayed out, because they are not supported in the currently selected configura‐
tion.
6. Turn on the necessary transmitter options.
Some options may be grayed out, because they are not supported in the currently selected configura‐
tion.
7. Select the example design options, (if you are generating the design example for Arria 10 devices).
8. Click Finish.
Related Information
SDI II IP Core Parameters on page 3-6
Generating a Design Example and Simulation Testbench
After you have parameterized the IP core, click Generate Example Design to create the following entities:
• design example— serves as a common entity for simulation and hardware verification.
• simulation testbench—consists of the design example entity and other non-synthesizable components.
The example testbench and the automated script are located in the <variation name>_example/
simulation/verilog or <variation name>_example/simulation/vhdl directory.
Note: Generating a design example can increase processing time.
You can now integrate your custom IP core variation into your design, simulate, and compile.
Simulating the SDI II IP Core Design
After design generation, the files located in the <variation name>_example/simulation/verilog or
<variation name>_example/simulation/vhdl directory are available for you to simulate your design.
The SDI II IP core supports the following EDA simulators listed in the table below.
Table 3-1: Supported EDA Simulators
Simulator Supported Platform Supported Language
ModelSim-SE Windows/Linux VHDL and Verilog HDL
ModelSim-Altera Windows/Linux Verilog
VCS/VCS MX Windows/Linux Verilog
UG-01125
2015.05.04
Parameterizing the IP Core 3-3
SDI II IP Core Getting Started Altera Corporation
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