Altera SDI II MegaCore - Manual (Page 25)

Figure 3-1: Design Example Entity and Simulation Testbench for Arria 10 Devices
Loopback
Path
Ch0 Loopback
(SDI TX + RX)
Arria 10 Native
PHY (Duplex)
Ch0 RX
Transceiver
Reset Controller
Pattern
Generator
Ch1 DUT
(SDI TX)
Arria 10 Native
PHY (TX)
Ch1 RX
Transceiver
Reset Controller
Ch0 TX
Transceiver
Reset Controller
Ch1 TX
Transceiver
Reconfiguration
Controller
Ch0 TX
PLL
Ch1 Test
(SDI RX)
Arria 10 Native
PHY (RX)
Ch0 TX
Transceiver
Reset Controller
Ch0 Duplex
Transceiver
Reconfiguration
Controller
Ch0 TX
PLL
Ch1 RX
Transceiver
Reconfiguration
Controller
TX Checker
RX
Checker
Test
Control
Testbench
Example Design
Data
Control
SDI II IP Core
Arria 10 Native PHY IP Core
Transceiver PHY Reset Controller IP Core
Arria 10 Transceiver CMU/ATX PLL IP Core
3-10 Design Examples for Arria 10 Devices
UG-01125
2015.05.04
Altera Corporation SDI II IP Core Getting Started
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