Altera SDI II MegaCore - Manual (Page 47)

Figure 4-7: Triple Rate SDI Transmitter Data Path Block Diagram
Match
TRS
Insert
Line
Scrambler
Insert
Line
20
Multiplexer
20 20
TX
Oversample
Generate
Clock Enable
TX PHY Management
& PHY Adapter
20 20
Transmit
TX Protocol Transceiver
Parallel
Video In
10
SDI Out
10
Insert
CRC
Insert
CRC
10
Insert
Payload ID 10
10 10 10 10
Insert
Payload ID
Match
TRS
Insert
Line
Insert
Line
10
Insert
CRC
Insert
CRC
10 10
10 10 10
C Link A
(3 Gb)
C Link B
(3 Gb)
Demultiplexer
Y or
Y Link A
(3 Gb)
C or
Y Link B
(3 Gb)
Convert
SD Bits
UG-01125
2015.05.04
Transmitter 4-5
SDI II IP Core Functional Description Altera Corporation
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