Contents
SDI II IP Core Quick Reference..........................................................................1-1
SDI II IP Core Overview......................................................................................2-1
General Description.....................................................................................................................................2-1
SMPTE372 Dual Link Support.......................................................................................................2-2
SMPTE RP168 Switching Support.................................................................................................2-6
SD 20-Bit Interface for Dual/Triple Standard..............................................................................2-6
Dynamic TX Clock Switching........................................................................................................2-7
Resource Utilization.................................................................................................................................... 2-9
SDI II IP Core Getting Started............................................................................3-1
Installation and Licensing...........................................................................................................................3-1
Design Walkthrough................................................................................................................................... 3-1
Creating a New Quartus II Project................................................................................................ 3-2
Launching IP Catalog...................................................................................................................... 3-2
Parameterizing the IP Core............................................................................................................ 3-3
Generating a Design Example and Simulation Testbench.........................................................3-3
Simulating the SDI II IP Core Design...........................................................................................3-3
Compiling the SDI II IP Core Design....................................................................................................... 3-4
Programming an FPGA Device................................................................................................................. 3-5
Design Reference..........................................................................................................................................3-5
SDI II IP Core Parameters.............................................................................................................. 3-6
SDI II IP Core Component Files....................................................................................................3-9
Design Examples.............................................................................................................................. 3-9
Video Pattern Generator Signals................................................................................................. 3-22
Transceiver Reconfiguration Controller Signals....................................................................... 3-23
Reconfiguration Management Parameters.................................................................................3-26
Reconfiguration Router Signals................................................................................................... 3-27
SDI II IP Core Functional Description...............................................................4-1
Protocol......................................................................................................................................................... 4-2
Transmitter....................................................................................................................................... 4-2
Receiver............................................................................................................................................. 4-6
Transceiver..................................................................................................................................................4-12
Submodules.................................................................................................................................................4-14
Insert Line....................................................................................................................................... 4-14
Insert/Check CRC..........................................................................................................................4-15
Insert Payload ID........................................................................................................................... 4-15
Match TRS...................................................................................................................................... 4-17
Scrambler........................................................................................................................................ 4-17
TOC-2
Altera Corporation
