Altera SDI II MegaCore User Manual

Page 3

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TX Sample.......................................................................................................................................4-18

Clock Enable Generator................................................................................................................4-18

RX Sample.......................................................................................................................................4-19

Detect Video Standard.................................................................................................................. 4-21

Detect 1 and 1/1.001 Rates............................................................................................................4-21

Transceiver Controller.................................................................................................................. 4-21

Descrambler....................................................................................................................................4-22

TRS Aligner.....................................................................................................................................4-23

3Gb Demux.....................................................................................................................................4-24

Extract Line.....................................................................................................................................4-24

Extract Payload ID.........................................................................................................................4-24

Detect Format.................................................................................................................................4-24

Sync Streams...................................................................................................................................4-25

Convert SD Bits..............................................................................................................................4-26

Insert Sync Bits...............................................................................................................................4-26

Clocking Scheme........................................................................................................................................4-27

SDI II IP Core Signals................................................................................................................................4-27

Additional Information......................................................................................A-1

Document Revision History......................................................................................................................A-1

TOC-3

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