Program a device, Program a device –14 – Altera HyperTransport MegaCore Function User Manual
Page 22
2–14
Chapter 2: Getting Started
Program a Device
HyperTransport MegaCore Function User Guide
© November 2009
Altera Corporation
5. Set the I/O Standard to HyperTransport for the I/O pins that are connected to the
HyperTransport wrapper ports
TxCAD_o[7:0]
,
TxCTL_o
,
TxClk_o
,
RxCAD_i[7:0]
,
RxCTL_i
, and
RxClk_i
, by performing the following steps:
a. In the row for the pin, double-click in the Assignment Name column.
b. In the Assignment Name list, click I/O Standard.
c. In the row for the pin, double-click in the Value column.
d. In the Value list, click HyperTransport.
6. Set the I/O Standard to 2.5 V for the I/O pins connected to the HyperTransport
wrapper ports
PwrOk
and
Rstn
.
7. If you are compiling the HyperTransport MegaCore function variation file
top-level entity in your Quartus II project, set virtual pin attributes for all of the
internal interface signals of the variation.
1
An example Quartus II project that has all of the above I/O standards set,
and virtual pin and clock latency settings, is included with the
HyperTransport MegaCore function installation. Refer to
Quartus II Project” on page 2–16
.
8. Turn on the Quartus II timing analysis setting Enable Clock Latency to perform
correct timing analysis. Refer to Quartus II Help for instructions on how to make
this assignment.
9. Set the remaining constraints in the Quartus II software, including the device, pin
assignments, timing requirements, and any other relevant constraints. Refer to
Appendix B, Stratix Device Pin Assignments
for more details about assigning
pins. If you have not made pin assignments for your board design, you can use the
Quartus II software to automatically assign pins.
10. On the Processing menu, click Start Compilation to compile the design.
Program a Device
After you compile your design, you can program your targeted Altera device and
verify your design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the
HyperTransport MegaCore function before you purchase a license. OpenCore Plus
evaluation allows you to generate an IP functional simulation model and produce a
time-limited programming file.
You can simulate the HyperTransport MegaCore function in your design and perform
a time-limited evaluation of your design in hardware.
1
For more information about OpenCore Plus hardware evaluation for the
HyperTransport MegaCore function, refer to