Altera HyperTransport MegaCore Function - Manual (Page 74)

C–2 Appendix C: Example Design
General Description
HyperTransport MegaCore Function User Guide © November 2009 Altera Corporation
Preliminary
4. The CPU reads the DMA status registers using an Rx non-posted read request and
subsequent HyperTransport Tx read response. The response informs it that the
operation has completed and it can program another DMA operation.
HyperTransport ordering rules ensure that the status register read response does
not pass the final DMA posted write, and the host CPU can be confident that all of
the DMA data has been written to host memory.
For a data movement that reads data from host CPU memory and writes to the
SDRAM the following sequence of events occurs:
1. The host CPU programs the DMA control registers using HyperTransport posted
writes. The writes come from the Rx posted interface and update the DMA control
registers.
2. The DMA state machine issues a read request to the HyperTransport interface
through the Tx non-posted buffer. To hide the latency of accessing memory on the
HyperTransport host CPU complex, the DMA state machine streams many read
requests without waiting for the responses. Each read request uses a unique source
tag in the HyperTransport request packet. (The source tag is set by the DMA state
machine, not by the HyperTransport MegaCore function.) A single read request
may not straddle a 64-byte boundary in the HyperTransport address space.
3. When the HyperTransport read responses begin arriving, the DMA state machine
reads the read response command packet from the Rx response buffer and uses the
returned source tag to determine the local SDRAM address. The SDRAM address
and write control is transferred to the SDRAM control. The read response data
packet is read from the Rx Response buffer and passed to the SDRAM control.
SDRAM control performs the SDRAM write.
4. Steps 2 and 3 repeat until the requested DMA transfer completes and all of the
read response data is returned and written to SDRAM.
5. The CPU reads the DMA status registers using an Rx non-posted read request and
subsequent HyperTransport Tx read response. The read response informs it that
the operation has completed and it can program another DMA operation.