Opencore plus evaluation, Performance, Opencore plus evaluation –3 – Altera HyperTransport MegaCore Function User Manual

Page 7: Performance –3

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Chapter 1: About this MegaCore Function

1–3

Performance

Altera Corporation

HyperTransport MegaCore Function User Guide

Preliminary

■

32-bit and 64-bit support across all base address registers (BARs)

■

Automatically handles all CSR space accesses

■

Verilog HDL and VHDL simulation support

OpenCore Plus Evaluation

With the Altera free OpenCore Plus evaluation feature, you can perform the following
actions:

■

Simulate the behavior of a megafunction (Altera MegaCore function or AMPP

™

megafunction) within your system

■

Verify the functionality of your design, as well as quickly and easily evaluate its
size and speed

■

Generate time-limited device programming files for designs that include
MegaCore functions

■

Program a device and verify your design in hardware

You only need to purchase a license for the MegaCore function when you are
completely satisfied with its functionality and performance, and want to take your
design to production.

For more information about OpenCore Plus hardware evaluation using the
HyperTransport MegaCore function, refer to

“OpenCore Plus Time-Out Behavior” on

page 3–40

and

AN 320: OpenCore Plus Evaluation of Megafunctions

Performance

The HyperTransport MegaCore function uses 20 differential I/O pin pairs and 2
single-ended I/O pins, requiring 42 pins total.

Table 1–3

through

Table 1–5

show

typical performance and adaptive look-up table (ALUT) or logic element (LE) usage
for the HyperTransport MegaCore function in Stratix II GX, Stratix II, Stratix, and
Stratix GX devices respectively, using the Quartus

II software version 7.1.

Table 1–3

shows the maximum supported data rates in megabits per second (Mbps)

by device family and speed grade.

Table 1–3. Maximum Supported HyperTransport Data Rates

(Note 1)

Device Family

Speed Grade

-3

-4

-5

-6