Altera HyperTransport MegaCore Function - Manual (Page 39)

Chapter 3: Specifications 3–13
HyperTransport MegaCore Function Specification
© November 2009 Altera Corporation HyperTransport MegaCore Function User Guide
Preliminary
When the attached HT device has a limited number of Rx buffers (on the order of four
or less), you can adjust the HyperTransport MegaCore function clocking option to
minimize the loop time. In this case, the flow control loop time is critical for
maintaining high throughput on HT link traffic transmitted from the HyperTransport
MegaCore function. By adjusting the clocking option, you can remove either the Tx
FIFO buffer or both the Tx and Rx FIFO buffers. Removing one or both buffers
increases throughput by removing the latency through the FIFO buffers. If you must
maintain maximum throughput on a single virtual channel with a small number of Rx
buffers, then use either the Shared Ref/Tx Clock or Shared Rx/Tx/Ref Clock option.
Using the Shared Ref/Tx Clock option removes the Tx FIFO buffer. Using the Shared
Rx/Tx/Ref Clock
option removes both the Tx and Rx FIFO buffers.
Refer to Table A–3 on page A–3 and Table A–4 on page A–3 for information about the
clocking option and Rx buffer size parameters.