Altera HyperTransport MegaCore Function User Manual
Page 72
B–2
Appendix B: Stratix Device Pin Assignments
Guidelines
HyperTransport MegaCore Function User Guide
© November 2009
Altera Corporation
Preliminary
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If you are using the Shared Ref/Tx Clock option, which requires separate transmit
and receive PLLs, and you are using a device with only four PLLs (for example,
the EP1S10, EP1S20, EP1S25, EP1S30 devices in 780-pin BGA packages, or the
EP1S40 in 780-pin BGA packages), the Rx and Tx interfaces must be in separate
I/O banks because these devices have only one PLL per differential I/O bank.
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If you are using the Shared Ref/Tx Clock option, which requires separate transmit
and receive PLLs, and you are using a Stratix device that has 8 PLLs (e.g., the
EP1S30 and EP1S40 devices in most packages, EP1S60, and EP1S80), the transmit
and receive interfaces can be placed in the same I/O bank because there are two
PLLs per differential I/O bank. You can also create an I/O pin out that supports
any clocking option with these devices. To support any clock option, the chosen
CAD
and
CTL
I/O pins must be clustered in the center of the I/O bank so that they
can be driven at a high speed from either the center or corner PLL. It is essential to
test your pin out with Quartus II compilation for all clock options you might use
before finalizing the pin out for board layout.
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If your HyperTransport interface is running at 300 MHz (600 Mbps) or 400 MHz
(800 Mbps), use only the pins listed as supporting a DIFFIO speed of “HIGH” in
the Stratix device pin information. This information is available on the Altera
website as part of the
.