Fpga configuration, Fpga programming over embedded usb-blaster ii, Fpga configuration –10 – Altera Cyclone V E FPGA Development Board User Manual

Page 18: Fpga programming over embedded usb-blaster ii –10

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2–10

Chapter 2: Board Components

FPGA Configuration

Cyclone V E FPGA Development Board

March 2013

Altera Corporation

Reference Manual

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System
Controller device programming methods supported by the Cyclone V E FPGA
development board.

The Cyclone V E FPGA development board supports the following configuration
methods:

■

Embedded USB-Blaster II is the default method for configuring the FPGA using
the Quartus II Programmer in JTAG mode with the supplied USB cable.

■

Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the program configuration
push button (S1).

■

External USB-Blaster for configuring the FPGA using an external USB-Blaster that
connects to the JTAG chain header (J4).

■

EPCQ device for serial or quad-serial FPGA configuration that supports AS x1 or
AS x4 configuration schemes.

FPGA Programming over Embedded USB-Blaster II

This configuration method implements a USB type-B connector (J10), a USB 2.0 PHY
device (U18), and an Altera MAX II CPLD EPM570GF100I5N (U16) to allow FPGA
configuration using a USB cable. This USB cable connects directly between the USB
type-B connector on the board and a USB port of a PC running the Quartus II
software.

The embedded USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally
masters the JTAG chain.

USB_CFG4

2.5-V