Altera Cyclone V E FPGA Development Board - Manual (Page 21)

Chapter 2: Board Components 2–13
FPGA Configuration
March 2013 Altera Corporation Cyclone V E FPGA Development Board
Reference Manual
FPGA Programming from Flash Memory
Flash memory programming is possible through a variety of methods. The default
method is to use the factory design—Board Update Portal. This design is an
embedded webserver, which serves the Board Update Portal web page. The web page
allows you to select new FPGA designs including hardware, software, or both in an
industry-standard S-Record File (.flash) and write the design to the user hardware
page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the development kit. The development board implements the Altera PFL
megafunction for flash memory programming. The PFL megafunction is a block of
logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This
pre-built design contains the PFL megafunction that allows you to write either page 0,
page 1, or other areas of flash memory over the USB interface using the Quartus II
software. This method is used to restore the development board to its factory default
settings.
Other methods to program the flash memory can be used as well, including the
Nios
® II processor.
f For more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
On either power-up or by pressing the program configuration push button,
PGM_CONFIG
(S1), the MAX V CPLD 5M2210 System Controller's PFL configures the
FPGA from the flash memory. The PFL megafunction reads 16-bit data from the flash
memory and converts it to fast passive parallel (FPP) format. This 16-bit data is then
written to the dedicated configuration pins in the FPGA during configuration.
Pressing the PGM_CONFIG push button (S1) loads the FPGA with a hardware page
based on which PGM_LED[2:0] (D25, D26, D27) illuminates.
Table 2–6 lists the design
that loads when you press the PGM_CONFIG push button.
Table 2–6. PGM_LED Settings (1)
PGM_LED0 (D25) PGM_LED1 (D26) PGM_LED2 (D27) Design
ON OFF OFF Factory hardware
OFF ON OFF User hardware 1
OFF OFF ON User hardware 2
Note to Table 2–6 :
(1) ON indicates a setting of ’0’ while OFF indicates a setting of ’1’.