Altera Cyclone V E FPGA Development Board User Manual
Page 48
2–40
Chapter 2: Board Components
Memory
Cyclone V E FPGA Development Board
March 2013
Altera Corporation
Reference Manual
E6
FLASH_CLK
N12
2.5-V
Clock
F8
FLASH_OEN
L11
2.5-V
Output enable
F7
FLASH_RDYBSYN
J12
2.5-V
Ready
D4
FLASH_RESETN
K11
2.5-V
Reset
G8
FLASH_WEN
P12
2.5-V
Write enable
C6
FLASH_WPN
—
2.5-V
Write protect
A1
FSM_A1
B11
2.5-V
Address bus
B1
FSM_A2
A11
2.5-V
Address bus
C1
FSM_A3
D9
2.5-V
Address bus
D1
FSM_A4
C10
2.5-V
Address bus
D2
FSM_A5
A10
2.5-V
Address bus
A2
FSM_A6
A9
2.5-V
Address bus
C2
FSM_A7
C9
2.5-V
Address bus
A3
FSM_A8
B8
2.5-V
Address bus
B3
FSM_A9
B7
2.5-V
Address bus
C3
FSM_A10
A8
2.5-V
Address bus
D3
FSM_A11
B6
2.5-V
Address bus
C4
FSM_A12
A6
2.5-V
Address bus
A5
FSM_A13
C7
2.5-V
Address bus
B5
FSM_A14
C6
2.5-V
Address bus
C5
FSM_A15
F13
2.5-V
Address bus
D7
FSM_A16
E13
2.5-V
Address bus
D8
FSM_A17
A5
2.5-V
Address bus
A7
FSM_A18
A4
2.5-V
Address bus
B7
FSM_A19
J7
2.5-V
Address bus
C7
FSM_A20
H7
2.5-V
Address bus
C8
FSM_A21
J9
2.5-V
Address bus
A8
FSM_A22
H9
2.5-V
Address bus
G1
FSM_A23
G9
2.5-V
Address bus
H8
FSM_A24
F8
2.5-V
Address bus
B6
FSM_A25
E8
2.5-V
Address bus
B8
FSM_A26
D8
2.5-V
Address bus
F2
FSM_D0
F16
2.5-V
Data bus
E2
FSM_D1
E16
2.5-V
Data bus
G3
FSM_D2
M9
2.5-V
Data bus
E4
FSM_D3
M8
2.5-V
Data bus
E5
FSM_D4
F15
2.5-V
Data bus
G5
FSM_D5
E15
2.5-V
Data bus
G6
FSM_D6
E12
2.5-V
Data bus
Table 2–28. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference (U10)
Schematic Signal Name
Cyclone V E FPGA
Pin Number
I/O Standard
Description