Altera Stratix III Development Board - Manual (Page 22)

2–14 Chapter 2: Board Components
MAX II CPLD
Stratix III 3SL150 Development Board May 2013 Altera Corporation
Reference Manual
C8 FTDI USB read enable USB_RDn 2.5 V — U11 pin 16
A6 FTDI USB write enable USB_WR 2.5 V — U11 pin 15
A5 FTDI USB reset USB_RSTn 2.5 V — U11 pin 4
D7 FTDI USB reset output USB_RSTOUTn 2.5 V — U11 pin 5
K12 FTDI USB power enable USB_PWR_ENn 1.8 V — U11 pin 10
D2
MAX II output to power seven
segment display
PWR_SEG_A 2.5 V — U27 pin 12
E5
MAX II output to power
7-segment display
PWR_SEG_B 2.5 V — U27 pin 11
D1
MAX II output to power
7-segment display
PWR_SEG_C 2.5 V — U27 pin 3
F3
MAX II output to power
7-segment display
PWR_SEG_D 2.5 V — U27 pin 8
E2
MAX II output to power
7-segment display
PWR_SEG_E 2.5 V — U27 pin 2
F4
MAX II output to power
7-segment display
PWR_SEG_F 2.5 V — U27 pin 9
E10
MAX II output to power
7-segment display
PWR_SEG_G 2.5 V — U27 pin 7
F5
MAX II output to power
7-segment display
PWR_SEG_DP 2.5 V — U27 pin 5
F2
MAX II output to power
7-segment display
PWR_SEG_MINUS 2.5 V — U27 pin 13
F6
MAX II output to power
7-segment display
PWR_DIG_SEL1 2.5 V — U27 pin 1
F1
MAX II output to power
7-segment display
PWR_DIG_SEL2 2.5 V — U27 pin 10
G3
MAX II output to power
7-segment display
PWR_DIG_SEL3 2.5 V — U27 pin 4
G2
MAX II output to power
7-segment display
PWR_DIG_SEL4 2.5 V — U27 pin 6
H5
Chip select to the power monitor
A/D
PMON_CSN 2.5 V — U18 pin 7
J1
Clock to/from the power
monitor A/D
PMON_CLK 2.5 V —
U18 pin 9 and U19,
pin 19
H4
Data from the power monitor
A/D
PMON_SDI 2.5 V — U18 pin 8
H3
Data to the power monitor
multiplexer
PMON_DATA 2.5 V — U19 pin 19
J2
Frame synchronization signal to
the power monitor multiplexer
PMON_SYNC 2.5 V — U19 pin 17
J16 Power selection input PWR_SEL0 1.8 V — SW6 pin P1
J13 Power selection input PWR_SEL1 1.8 V — SW6 pin P2
Table 2–5. MAX II Device Pin-out (Part 7 of 9)
MAX II
Pin Number
Description Schematic Signal Name
I/O
Standard
Stratix III
Pin
Number
Other Connections