Texas Instruments TMS320C645x DSP - Manual (Page 113)

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5.29 MAC Control Register (MACCONTROL)
EMAC Port Registers
The MAC control register (MACCONTROL) is shown in Figure 57 and described in Table 57 .
Figure 57. MAC Control Register (MACCONTROL)
31 24
Reserved
R-0
23 19 18 17 16
Reserved RGMIIEN GIGFORCE RMIIDUPLEX-
MODE
R-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
RMIISPEED RXOFFLENBLOCK RXOWNERSHIP RXFIFO CMDIDLE Reserved TXPTYPE Reserved
FLOWEN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R-0
7 6 5 4 3 2 1 0
GIG TXPACE GMIIEN TXFLOWEN RXBUFFERFLOWEN Reserved LOOPBACK FULLDUPLEX
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 57. MAC Control Register (MACCONTROL) Field Descriptions
Bit Field Value Description
31-19 Reserved 0 Reserved
18 RGMIIEN RGMII enable bit. Enables the fullduplex and gigabit mode to be selected from the
RGMIIFULLDUPLEX and RGMIIGIG input signals and not from the FULLDUPLEX and GIG bits
contained in this register. This bit is directly connected to the RXINBAND input on the RGMII
module.
0 The RGMII interface is in forced link mode. The duplexity is determined by the FULLDUPLEX
bit, and the speed is determined by the GIG bit. The speed is either 1 Gbps or 100 Mbps; 10
Mbps is not supported in forced link mode.
1 The RGMII interface requires and uses the in-band signals coming in on its receive.
17 GIGFORCE Gigabit force mode. This bit is used to force the EMAC into gigabit mode if the input MTCLK
signal has been stopped by the PHY.
16 RMIIDUPLEXMODE Duplex mode for the RMII interface.
0 The RMII operates in half duplex mode
1 The RMII operates in full duplex mode. This mode is not supported in the C645x devices.
15 RMIISPEED Operating speed for the RMII interface
0 The RMII operates at 2.5 MHz (10Mbps mode)
1 The RMII operates at 25 MHz (100 Mbps mode)
14 RXOFFLENBLOCK Receive offset / length word write block
0 Do not block the DMA writes to the receive buffer descriptor offset/buffer length word
1 Block all EMAC DMA controller writes to the receive buffer descriptor offset/buffer length words
during packet processing. When this bit is set, the EMAC will never write the third word to any
receive buffer descriptor.
13 RXOWNERSHIP Receive ownership write bit value
0 The EMAC writes the Receive ownership bit to zero at the end of packet processing
1 The EMAC writes the Receive ownership bit to one at the end of packet processing. If you do
not use the ownership mechanism, you can set this mode to preclude the necessity of software
having to set this bit each time the buffer descriptor is used.
12 RXFIFOFLOWEN Receive FIFO flow control enable
0 Receive flow control disabled. For full-duplex mode, no outgoing pause frames are sent.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 113
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