Descriptions, Section 5.48 – Texas Instruments TMS320C645x DSP User Manual
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5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)
EMAC Port Registers
The Transmit Channel 0-7 Completion Pointer Register (TXnCP) is shown in
and described in
Figure 76. Transmit Channel n Completion Pointer Register (TXnCP)
31
16
TXnCP
R/W-x
15
0
TXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset
Table 76. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit
Field
Value
Description
31-0
TXnCP
Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
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SPRU975B – August 2006