Texas Instruments TMS320C645x DSP - Manual (Page 37)

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2.6 EMAC Control Module
Arbiter and
bus switches
CPU
DMA Controllers
8K byte
descriptor
memory
Configuration
registers
Interrupt
logic
Single interrupt
to CPU
EMAC interrupts
MDIO interrupts
Configuration bus
Transmit and Receive
2.6.1 Internal Memory
2.6.2 Bus Arbiter
EMAC Functional Architecture
The EMAC control module ( Figure 11 ) interfaces the EMAC and MDIO modules to the rest of the system,
and provides a local memory space to hold EMAC packet buffer descriptors. Local memory is used to
avoid contention to device memory spaces. Other functions include the bus arbiter, and interrupt logic
control.
Figure 11. EMAC Control Module Block Diagram
The control module includes 8K bytes of internal memory. The internal memory block allows the EMAC to
operate more independently of the CPU. It also prevents memory underflow conditions when the EMAC
issues read or write requests to descriptor memory. (The EMAC's internal FIFOs protect memory
accesses to read or write actual Ethernet packet data.)
A descriptor is a 16-byte memory structure that holds information about a single Ethernet packet buffer,
which may contain a full or partial Ethernet packet. Thus, with the 8K memory block provided for
descriptor storage, the EMAC module can send and receive up to a combined 512 packets before it must
be serviced by application or driver software.
The control module’s bus arbiter operates transparently to the rest of the system. It arbitrates between the
device core and EMAC buses for access to internal descriptor memory, and arbitrates between internal
EMAC buses for access to system memory.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 37
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