Hdp), Descriptions, Section 5.47 – Texas Instruments TMS320C645x DSP User Manual
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5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)
EMAC Port Registers
The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in
and
described in
Figure 75. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
31
16
RXnHDP
R/W-x
15
0
RXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset
Table 75. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions
Bit
Field
Value
Description
31-0
RXnHDP
Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor address
to this location allows receive DMA operations in the selected channel when a channel frame is
received. Writing to these locations when they are nonzero is an error (except at reset). Host
software must initialize these locations to zero on reset.
SPRU975B – August 2006
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
133