Texas Instruments TMS320C645x DSP - Manual (Page 72)

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4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
MDIO Registers
The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 21 and
described in Table 20 .
Figure 21. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
31 16
Reserved
R-0
15 2 1 0
Reserved LINKINT
MASKED
R-0 R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 20. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field
Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1-0 LINKINTMASKED MDIO Link change interrupt, masked value. . When asserted, a bit indicates that there was an
MDIO link change event (i.e. change in the LINK register) corresponding to the PHY address in the
USERPHYSEL register and the corresponding LINKINTENB bit was set. LINKINTRAW[0] and
LINKINTRAW[1] correspond to USERPHYSEL0 and USERPHYSEL1, respectively. Writing a 1 will
clear the event and writing 0 has no effect.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 72 SPRU975B – August 2006
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