Texas Instruments TMS320C645x DSP - Manual (Page 75)

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4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
MDIO Registers
The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in
Figure 24 and described in Table 23 .
Figure 24. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
31 16
Reserved
R-0
15 2 1 0
Reserved USERINT
MASKSET
R-0 R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 23. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field
Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1-0 USERINTMASKSET MDIO user interrupt mask set for USERINTMASKED[1:0] respectively. Setting a bit to 1 will
enable MDIO user command complete interrupts for that particular USERACCESS register.
MDIO user interrupt for a particular USERACCESS register is disabled if the corresponding bit
is 0. Writing a 0 to this register has no effect.
SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 75
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