Userintmaskclear), Section 4.11 – Texas Instruments TMS320C645x DSP User Manual
Page 76
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4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
MDIO Registers
The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in
and described in
.
Figure 25. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
31
16
Reserved
R-0
15
2
1
0
Reserved
USERINTMASK
CLEAR
R-0
R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 24. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Field Descriptions
Bit
Field
Value
Description
31-2
Reserved
0
Reserved
1-0
USERINTMASK
MDIO user command complete interrupt mask clear for USERINTMASKED[1:0] respectively.
CLEAR
Setting a bit to 1 will disable further user command complete interrupts for that particular
USERACCESS register. Writing a 0 to this register has no effect.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
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SPRU975B – August 2006