Cirrus Logic CS4970x4 - Manual (Page 17)

P-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6
Firmware Overview
CS4953x4/CS4970x4 System Designer’s Guide
P.3.11 DMA Controller
The DMA controller contains 12 stereo channels. The O/S uses 11 stereo channels, 6 for the DAO (2 are
for the S/PDIF transmitters), 4 for the DAI, and one for the parallel control port. The addition of the DMA
channel for the parallel control port allows compressed audio data to be input over this port. The DMA
block is able to move data to/from X or Y memory, or alternate between both X and Y memory. The DMA
controller moves data to/from X and/or Y memory opportunistically (if the core is not currently accessing
that particular memory space during the current cycle). The DMA controller has a “Dead Man’s” timer so
that if the core is running an inner loop and accessing memory every cycle, the DMA controller can
interrupt the core to run a DMA cycle.
P.3.12 Timers
A 32-bit timer block runs off the CS4953x4/CS4970x4 DSP clock. The timer count decrements with each
clock tick of the DSP clock when the timer is enabled. When the timer count reaches zero, it is re-
initialized, and may be programmed to generate an interrupt to the DSP.
P.3.13 Clock Manager and PLL
The CS4953x4/CS4970x4 Clock Manager and PLL module contains an Analog PLL, RTL Clock
Synthesizer, and Clock Manager. The Analog PLL is a customized analog hard macro that contains the
Phase Detector (PD), Charge Pump, Loop Filter, VCO, and other non-digital PLL logic. The Clock
Synthesizer is a digital design wrapper around the analog PLL that allows clock frequency ranges to be
programmed. The Clock Manager is a digital design wrapper for the Clock Synthesizer that provides the
logic (control registers) necessary to meet chip clocking requirements.
The Clock Manager and PLL module generates two Master clocks:
• Global chip clock (clocks the DSP core, internal memories, SDRAM, Flash, and all peripherals)
• Oversampled audio clock. This clock feeds the DAO block which has dividers to generate the
DAO_MCLK, DAO_SCLK, and DAO_LRCLK.
P.3.14 Programmable Interrupt Controller
The Programmable Interrupt Controller (PIC) forces all incoming interrupts to be synchronized to the
global clock, HCLK. The PIC provides up to 16 interrupts to the DSP Core. The interrupts are prioritized
with interrupt 0 as the highest priority and interrupt 15 as the lowest priority. Each interrupt has a
corresponding interrupt address that is also supplied to the DSP core. The interrupt address is the same
as the IRQ number (interrupt 0 uses interrupt address 0 and interrupt 15 uses interrupt address 15). Both
an enable mask and a run mask are provided for each interrupt. The enable mask allows the enabled
interrupts to generate a PIC_REQ signal to the DSP core, and the run mask allows the enabled interrupts
to generate a PIC_CLR, thereby bringing the core out of its halt state when it accepts the interrupt.
P.4 Firmware Overview
P.4.1 Robust DSP Manager Firmware API
Cirrus Logic includes a robust firmware API to allow customers to develop DSP applications with a
smaller microcontroller code set than was necessary in previous Cirrus Logic DSP products. See
Chapter
7, "Overview of Common Firmware Modules" for information about the new DSP Manager firmware API
from Cirrus Logic.