5 i2c read procedure, 5 i2c read procedure -18, D in – Cirrus Logic CS4970x4 User Manual

Page 64: Section 2.5.3.5

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I2C Port

CS4953x4/CS4970x4 System Designer’s Guide

DS810UM6

Copyright 2013 Cirrus Logic, Inc

2-18

2.5.3.5 I

2

C Read Procedure

1.

An I

2

C

read transaction is initiated by CS4953x4/CS4970x4 driving SCP1_IRQ low, signaling that it

has data to be read.

2. The Master responds by sending an I

2

C

Start condition which is SCP1_SDA going low while

SCP1_CLK is held high.

3. This is followed by a 7-bit address and the read/write bit set high for a read. So, the Master should

send 0x81. The 0x81 byte represents the 7-bit I

2

C address 1000000b, and the least significant bit set

to ‘1’, designates a read.

4. After the address byte, the Master must release the data line and provide a ninth clock for the

CS4953x4/CS4970x4 DSP (Slave) to acknowledge (ACK) receipt of the byte. The CS4953x4/
CS4970x4 will drive the data line low during the ninth clock to acknowledge. If for some reason
CS4953x4/CS4970x4 does not acknowledge (NACK), it means that the communications channel has
been corrupted and the CS4953x4/CS4970x4 should be re-booted. A NACK should never happen
here.

5. The data is ready to be clocked out on the SCP1_SDA line at this point. Data clocked out by the host

is valid on the rising edge of SCP1_CLK and data transitions occur just after the falling edge of
SCP1_CLK.

6. After the CS4953x4/CS4970x4 has written the byte to the Master on the SCP1_SDA line, it will

release the SCP1_SDA line. If the Master has more bytes in the 4-byte word to read, then proceed to
Step 7. If the Master is finished reading all bytes of the 4-byte word, then proceed to Step 8.

7. The Master should drive the SCP1_SDA line low for the 9

th

SCP1_CLK clock to acknowledge (ACK)

that the byte was received from the CS4953x4/CS4970x4. The Master should then return to Step 5 to
read another byte of the 4-byte word.

8. If SCP1_IRQ is still low after reading a 4-byte word, proceed to Step 7. If SCP1_IRQ has risen,

proceed to Step 9.

9. The Master should let the SCP1_SDA line stay high for the 9th SCP1_CLK clock as a no-

acknowledge (NACK) to CS4953x4/CS4970x4. This, followed by an I

2

C stop condition (SCP1_SDA

driven high, while SCP1_CLK is high) signals an end of read to CS4953x4/CS4970x4. See

Section

2.4.3.5 on page 2-9

for an in-depth explanation of SCP1_IRQ.

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