Cirrus Logic CS4970x4 - Manual (Page 91)

5-6 Copyright 2013 Cirrus Logic, Inc. DS810UM6
SPI Flash Interface
CS4953x4/CS4970x4 System Designer’s Guide
5.2 SPI Flash Interface
The CS4953x4/CS4970x4 provides a glueless external Serial Peripheral Interface (SPI) Flash interface
that supports connection to an external SPI Flash or EEPROM for code storage. This allows for products
to be field-upgraded as new audio algorithms are developed. The SPI Flash interface allows autobooting
from a SPI Flash device. Coefficients for filters may also be stored and recalled from SPI Flash.
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DynamictRRD
Configure the active bank A to active bank B latency
Bit 31:4 = 0 = Reserved
Bit 3:0 = Trrd, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF= 16 DSP clk cycles.
Example:
Trrd = 15 nS, HCLK = 150 MHz
Trrd = 15 nS * 150 MHz - 1= 2.25 - 1 = 0x2
0x8100006B
0xhhhhhhhh
Default 0x00000001
DynamictMRD
Configure the load mode register to active command time. Also known as Trsa
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tmrd, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF= 16 DSP clk cycles.
Example:
Tmrd = 1CLK (6.7 nS), HCLK = 150MHz
Tmrd = 1-1 = 0x0
0x8100006C
0xhhhhhhhh
Default 0x00000000
DynamicConfig0
Configure the active bank A to active bank B latency
Bit 31:12 = 0 = Reserved
Bit 11:7 = External bus address mapping (Row, Bank, Column),where:
00001 = 16Mb (1Mx16), 2 banks, row length = 11, column length = 8
00101 = 64Mb (4Mx16), 4 banks, row length = 12, column length = 8
01001 = 128Mb (8Mx16), 4 banks, row length = 12, column length = 9
Bit 6:0 = 0 = Reserved
0x8100006E
0xhhhhhhhh
Default 0x00000280
DynamicRasCas0
Configure the active bank A to active bank B latency
Bit 31:10 = 0 = Reserved
Bit 9:8 = CAS latency (CAS),where:
00 = reserved
01 = one clock cycle
10 = two clock cycles
11 = three clock cycles
Bit 7:2 = 0 = Reserved, rCAS latency (CAS),where:
Bit 1:0 = RAS latency (RAS),where:
00 = reserved
01 = one clock cycle
10 = two clock cycles
11 = three clock cycles
0x8100006F
0xhhhhhhhh
Default 0x00000303
Table 5-2. SDRAM Interface Parameters (Continued)
Mnemonic Hex Message