Cirrus Logic CS4970x4 - Manual (Page 8)

viii Copyright 2013 Cirrus Logic, Inc. DS810UM6
CS4953x4/CS4970x4 System Designer’s Guide
C.1.5 Dolby Digital®PLus ....................................................................................................... C-3
C.1.5.1 Loading Dolby Digital Plus for Stereo Output............................................... C-3
C.1.5.2 Setting DRC Modes for Dolby Digial Plus .................................................... C-3
C.1.6 Dolby® TrueHD............................................................................................................. C-3
C.1.6.1 Loading Dolby TrueHD for Stereo Downmix Output .................................... C-3
C.1.6.2 Setting DRC Modes for Dolby TrueHD ........................................................ C-4
C.1.7 Dolby ProLogic® IIx ...................................................................................................... C-4
C.1.7.1 Loading Dolby ProLogic IIx .......................................................................... C-4
C.1.7.2 Using Dolby ProLogic IIx to Output HD Audio Streams ............................... C-4
C.1.8 Dolby Virtual Speaker® 2.............................................................................................. C-5
C.1.8.1 Loading Dolby Virtual Speaker 2.................................................................. C-5
C.1.8.2 Loading Dolby Virtual Speaker 2 with Dolby ProLogic II .............................. C-5
C.1.8.3 Removing Dolby Virtual Speaker 2 .............................................................. C-5
C.1.9 Dolby Headphone® 2.................................................................................................... C-5
C.1.9.1 Loading Dolby Headphone 2........................................................................ C-5
C.1.9.2 Loading Dolby Headphone 2 with Dolby ProLogic II .................................... C-6
C.1.9.3 Removing Dolby Headphone 2 .................................................................... C-6
C.1.10 DTS-HD™ High Resolution Audio .............................................................................. C-6
C.1.10.1 Loading DTS-HD High Resolution Audio for Stereo Downmix Output ....... C-6
C.1.11 DTS-HD™ Master Audio............................................................................................. C-7
C.1.11.1 Loading DTS-HD Master Audio for Stereo Downmix Output ..................... C-7
C.1.12 Crossbar (Downmix and Upmix) ................................................................................. C-7
C.1.12.1 Loading Crossbar with Legacy and PCM Modules .................................... C-7
C.1.12.2 Loading Crossbar for Dual Zone Output with Logic 7 and HD Decoders... C-7
C.1.13 Intelligent Room Calibration 2 (IRC2) ......................................................................... C-8
C.1.13.1 Configuring the DSP for IRC2 .................................................................... C-8
Revision History ................................................................................................... C-9
Figures
Figure P-1. CS4970x4 Chip Functional Block Diagram .............................................................................. P-2
Figure P-2. CS4953x4 Chip Functional Block Diagram .............................................................................. P-3
Figure P-3. PLL Filter Topology .................................................................................................................. P-9
Figure P-4. Crystal Oscillator Circuit Diagram ........................................................................................... P-10
Figure 1-1. Operation Mode Block Diagram .................................................................................................1-1
Figure 1-2. CS497004, LQFP 144-Pin Package, SPI Control, Master Boot Typical Connection Diagram ..1-4
Figure 1-3. CS497004/CS4963x4, LQFP 128-Pin Package, SPI Control, Master Boot Typical Connection Diagram
1-5
Figure 1-4. Master Boot Flow .......................................................................................................................1-7
Figure 2-1. SPI Serial Control Port Internal Block Diagram .........................................................................2-2
Figure 2-2. Block Diagram of SPI System Bus .............................................................................................2-3
Figure 2-3. SPI Write Flow Diagram .............................................................................................................2-5
Figure 2-4. SPI Read Flow Diagram ............................................................................................................2-6
Figure 2-5. Sample Waveform for SPI Write Functional Timing ...................................................................2-8
Figure 2-6. Sample Waveform for SPI Read Functional Timing ..................................................................2-8