Cirrus Logic CS4970x4 - Manual (Page 62)

I2C Port
CS4953x4/CS4970x4 System Designer’s Guide
DS810UM6 Copyright 2013 Cirrus Logic, Inc 2-16
2.5.3.3 I
2
C Write Protocol
1. An I
2
C transfer is initiated with an I
2
C start condition which is defined as the data (SCP1_SDA) line
falling while the clock (SCP1_CLK) is held high.
2. This is followed by a 7-bit address and the read/write bit held low for a write. So, the Master should
send 0x80. The 0x80 byte represents the 7-bit I
2
C address 1000000b, and the least significant bit set
to ‘0’, designates a write.
3. After each byte (including the address and each data byte) the Master must release the data line and
provide a ninth clock for the CS4953x4/CS4970x4 DSP (Slave) to acknowledge (ACK) receipt of the
byte. The CS4953x4/CS4970x4 drive the data line low during the ninth clock to acknowledge. If for
some reason the CS4953x4/CS4970x4 does not acknowledge (NACK), it means that the
communications channel has been corrupted and the CS4953x4/CS4970x4 should be re-booted. A
NACK should never happen here.
4. The Master should then clock one data byte into the device, most-significant bit first.
5. The CS4953x4/CS4970x4 (Slave) will (and must) acknowledge (ACK) each byte that it receives
which means that after each byte, the Master must provide an acknowledge clock pulse on
SCP1_CLK and release the data line, SCP1_SDA.
6. If the Master has no more data words to write to the CS4953x4/CS4970x4, then proceed to Step 8. If
the Master has more data words to write to the CS4953x4/CS4970x4, then proceed to Step 7.
7. The Master should poll the SCP1_BSY signal until it goes high. If the SCP1_BSY signal is low, it
indicates that the CS4953x4/CS4970x4 is busy performing some task that requires pausing the serial
control port. Once the CS4953x4/CS4970x4 is able to receive more data words, the SCP1_BSY
signal will go high. Once the SCP1_BSY signal is high, proceed to Step 4.
Note: The DSP’s I
2
C port also implements clock stretching to indicate that the host should pause
communication. So the host has the option of checking for SCP1_CLK held low rather than
SCP1_BSY low.
8. At the end of a data transfer, a stop condition must be sent. The stop condition is defined as the rising
edge of SCP1_SDA while SCP1_CLK is high.
2.5.3.4 Performing a Serial I
2
C Read
Information provided in this section is intended as a functional description indicating how to use the
configured serial control port to perform an I
2
C read from an external device (Master) to the CS4953x4/
CS4970x4 DSP (Slave). The system designer must ensure that all timing constraints of the I
2
C Read
Cycle are met (see the CS4953x4/CS4970x4 datasheet for timing specifications). I
2
C read transactions
from the CS4953x4/CS4970x4 will always involve reading 4-byte words.
Figure 2-15 illustrates the sequence of events that define the I
2
C read protocol for SCP1. This protocol is
discussed in the high-level procedure found in Section 2.5.3.5.