Cirrus Logic CS4970x4 - Manual (Page 66)

2-20 Copyright 2013 Cirrus Logic, Inc. DS810UM6
I2C Port
CS4953x4/CS4970x4 System Designer’s Guide
2.5.3.6 SCP1_IRQ Behavior
Once the BOOT_ASSIST_A (.ULD file) has been downloaded in accordance to Steps 1 through 8 in
Section 2.3.1. or Steps 1 through 8 in Section 2.3.2. , the SCP1_IRQ pin is functionally enabled.
The SCP1_IRQ signal is not part of the I
2
C protocol, but is provided so that the Slave can signal that it has
data to be read. A high-to-low transition on SCP1_IRQ indicates to the Master that the Slave has data to
be read. When a Master detects a high-to-low transition on SCP1_IRQ, it should send a Start condition
and begin reading data from the Slave.
SCP1_IRQ is guaranteed to remain low (once it has gone low), until the falling edge of SCP1_CLK for the
last bit of the last byte to be transferred out of CS4953x4/CS4970x4 (that is, the rising edge of SCP1_CLK
before the ACK). If there is no more data to be transferred, SCP1_IRQ will go high at this point. After
going high, SCP1_IRQ is guaranteed to stay high until the next rising edge of SCP1_CLK (that is, it will
stay high until the rising edge of SCP1_CLK for the ACK/NACK bit).
This end-of-transfer condition signals the Master to end the read transaction by clocking the last data bit
out of CS4953x4/CS4970x4 and then sending a NACK to CS4953x4/CS4970x4 to signal that the read
sequence is over. At this point, the Master should send an I
2
C stop condition to complete the read
sequence. If SCP1_IRQ is still low after the rising edge of SCP1_CLK on the last data bit of the current
byte, the Master should send an acknowledge and continue reading data from the serial control port. It
should be noted that all data should be read out of the serial control port during one cycle or a loss of data
will occur. In other words, all data should be read out of the chip until SCP1_IRQ signals the last byte by
going high as described above.
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