DS810UM6
Copyright 2013 Cirrus Logic, Inc.
ix
CS4953x4/CS4970x4 System Designer’s Guide
Figure 2-7. Serial Control Port Internal Block Diagram ................................................................................2-9
Figure 2-8. Block Diagram of I2C System Bus ...........................................................................................2-10
Figure 2-9. I2C Start and Stop Conditions .................................................................................................2-11
Figure 2-10. I2C Address with ACK and NACK .........................................................................................2-12
Figure 2-11. Data Byte with ACK and NACK .............................................................................................2-13
Figure 2-12. Repeated Start Condition with ACK and NACK .....................................................................2-13
Figure 2-13. Stop Condition with ACK and NACK ......................................................................................2-14
Figure 2-14. I2C Write Flow Diagram .........................................................................................................2-15
Figure 2-15. I2C Read Flow Diagram .........................................................................................................2-17
Figure 2-16. Sample Waveform for I2C Write Functional TIming ...............................................................2-19
Figure 2-17. Sample Waveform for I2C Read Functional TIming ..............................................................2-19
Figure 3-1. DAI Port Block Diagram .............................................................................................................3-3
Figure 3-2. Left-justified Format (Rising Edge Valid SCLK) .........................................................................3-4
Figure 3-3. DSD Port Block Diagram ...........................................................................................................3-8
Figure 4-1. DAO Block Diagram ...................................................................................................................4-2
Figure 4-2. I2S Compatible Serial Audio Formats (Rising Edge Valid .........................................................4-3
Figure 4-3. Left-justified Digital Audio Formats (Rising Edge Valid DAO_SCLK) ........................................4-3
Figure 4-4. One-line Data Mode Digital Audio Formats ...............................................................................4-4
Figure 5-1. SDRAM Interface Block Diagram ...............................................................................................5-1
Figure 8-1. DSP Condenser-produced Control Code ...................................................................................8-1
Figure 8-2. DSP Condenser Wizard, General Page .....................................................................................8-4
Figure 8-3. DSP Condeser Wizard, Search paths Page ..............................................................................8-5
Figure 8-4. DSP Condenser Wizard, Audio sources Page ...........................................................................8-6
Figure 8-5. DSP Condenser Wizard, Sample Rates Page ...........................................................................8-7
Figure 8-6. DSP Condenser Wizard, Firmware components Page ..............................................................8-8
Figure 8-7. DSP Condenser Wizard, PPM modes Page ..............................................................................8-9
Figure 8-8. DSP Condenser Wizard, Stream types Page ..........................................................................8-10
Figure 8-9. DSP Condenser Wizard, Power-up state Page .......................................................................8-11
Figure 8-10. DSP Condenser Wizard, WAV update Page .........................................................................8-12
Figure 8-11. DSP Condenser Project Flash Memory Organization ............................................................8-16
Figure 8-12. DSP Composer Sample Project, “WhizBang Model” Directory Structure: .............................8-18
Figure 8-13. DSP Composer Snapshot ......................................................................................................8-19
Figure 8-14. Sample Deliverables Directory Struction ...............................................................................8-20
Figure 8-15. Blank SPI Flash Format .........................................................................................................8-21
Figure 8-16. Flash Image Creation Process Flow ......................................................................................8-22
Figure 8-17. New Project Window in DSP Condenser ...............................................................................8-23
Figure 8-18. DSP Condenser Flash Image Build Log ................................................................................8-24