Cirrus Logic CS4970x4 - Manual (Page 89)

5-4 Copyright 2013 Cirrus Logic, Inc. DS810UM6
SDRAM Controller
CS4953x4/CS4970x4 System Designer’s Guide
Table 5-2. SDRAM Interface Parameters
Mnemonic Hex Message
Extmem_Setup_Control
Bit 31:5 = 0 = Reserved
Bit 4 = 0/1 = Disable/Enable Flash port
Bit 3:1 = 0 = Reserved
Bit 0 = 0/1 = Disable/Enable SDRAM port
0x8100005C
0xhhhhhhhh
Default: 0x00000011
CRUSConfig
Bit 31:9 = 0 = Reserved
Bit 8 = Pin Mapping, where:
0 = Enable Flash and SDRAM Mapping
1 = Enable Flash and SRAM Mapping
Bit 7:0 = 0 = Reserved
0x8100005D
0xhhhhhhhh
Default: 0x00000000
DynamicRefresh
Configure the refresh period
Bit 31:11 = 0 = Reserved
Bit 10:0 = REFRESH, where:
0x0 = refresh disabled.
0x1 = 1x16 = 16 HCLK ticks between refresh cycles
0x8 = 8x16 = 128 HCLK ticks between refresh cycles
0x1 to 0x7FF = REFRESH*16 HCLK ticks between refresh cycles
Example:
Refresh Period = 15.625
S, HCLK = 10 MHz
REFRESH = (15.62 5
S*150MHz)/16 = 146.44 = 0x93
0x81000061
0xhhhhhhhh
Default 0x00000075
DynamictRP
Configure the precharge command period
Bit 31:4 = 0 = Reserved
Bit 3:0 = Trp, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
Example:
Trp = 20 nS, HCLK = 150 MHz
Trp =20 nS*150 MHz - 1 = 3 -1= 0x2
0x81000062
0xhhhhhhhh
Default 0x00000002
DynamictRAS
Configure the active to precharge command period
Bit 31:4 = 0 = Reserved
Bit 3:0 = Tras, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
Example:
Tras = 45 nS, HCLK = 150 MHz
Tras =45 nS*150 MHz - 1 = 6.75 -1= 0x6
0x81000063
0xhhhhhhhh
Default 0x00000004
DynamictREX
Configure the self refres exit time. Also known as Tsre
Bit 31:4 = 0 = Reserved
Bit 3:0 = Trex, where:
0x0 to 0xE = (n + 1) DSP clk cycles.
0xF = 16 DSP clk cycles.
Example:
Trex = 83 nS, HCLK = 150 MHz
Trex = 83 nS * 150 MHz - 1 =12.45 -1 = 0xC
0x81000064
0xhhhhhhhh
Default 0x00000009