Document Outline

• Altera Transceiver PHY IP Core User Guide
• Contents
• 1. Introduction to the Protocol-Specific and Native Transceiver PHYs
  • Protocol-Specific Transceiver PHYs
  • Native Transceiver PHYs
  • Non-Protocol-Specific Transceiver PHYs
  • Transceiver PHY Modules
  • Transceiver Reconfiguration Controller
  • Resetting the Transceiver PHY
  • Running a Simulation Testbench
  • Unsupported Features
• 2. Getting Started Overview
  • Installation and Licensing of IP Cores
  • Design Flows
  • MegaWizard Plug-In Manager Flow
    • Specifying Parameters
    • Simulate the IP Core
• 3. 10GBASE-R PHY IP Core
  • 10GBASE-R PHY Release Information
  • 10GBASE-R PHY Device Family Support
  • 10GBASE-R PHY Performance and Resource Utilization for Stratix IV Devices
  • 10GBASE-R PHY Performance and Resource Utilization for Arria V GT Devices
  • 10GBASE-R PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices
  • Parameterizing the 10GBASE-R PHY
  • General Option Parameters
  • Analog Parameters for Stratix IV Devices
  • 10GBASE-R PHY Interfaces
  • 10GBASE-R PHY Data Interfaces
  • 10GBASE-R PHY Status, 1588, and PLL Reference Clock Interfaces
  • Optional Reset Control and Status Interface
  • 10GBASE-R PHY Clocks for Arria V GT Devices
  • 10GBASE-R PHY Clocks for Arria V GZ Devices
  • 10GBASE-R PHY Clocks for Stratix IV Devices
  • 10GBASE-R PHY Clocks for Stratix V Devices
  • 10GBASE-R PHY Register Interface and Register Descriptions
  • 10GBASE-R PHY Dynamic Reconfiguration for Stratix IV Devices
  • 10GBASE-R PHY Dynamic Reconfiguration for Arria V and Stratix V Devices
  • 1588 Delay Requirements
  • 10GBASE-R PHY TimeQuest Timing Constraints
  • 10GBASE-R PHY Simulation Files and Example Testbench
• 4. Backplane Ethernet 10GBASE-KR PHY IP Core with Early Access FEC Option
  • 10GBASE-KR PHY Release Information
  • Device Family Support
  • 10GBASE-KR PHY Performance and Resource Utilization
  • Parameterizing the 10GBASE-KR PHY
    • 10GBASE-KR Link Training Parameters
    • 10GBASE-KR Auto-Negotiation and Link Training Parameters
    • 10GBASE-R Parameters
    • 1GbE Parameters
    • Speed Detection Parameters
    • PHY Analog Parameters
  • 10GBASE-KR PHY IP Core Functional Description
  • 10GBASE-KR PHY Arbitration Logic Requirements
  • 10GBASE-KR PHY State Machine Logic Requirements
  • Forward Error Correction (Clause 74)
  • 10BASE-KR PHY Interfaces
  • 10GBASE-KR PHY Clock and Reset Interfaces
    • 10GBASE-KR PHY Data Interfaces
      • 10GBASE-KR PHY XGMII Mapping to Standard SDR XGMII Data
      • 10GBASE-KR PHY Serial Data Interface
    • 10GBASE-KR PHY Control and Status Interfaces
    • Daisy-Chain Interface Signals
    • Embedded Processor Interface Signals
    • Dynamic Reconfiguration Interface Signals
  • Register Interface Signals
  • 10GBASE-KR PHY Register Definitions
  • PMA Registers
  • PCS Registers
  • Creating a 10GBASE-KR Design
  • Editing a 10GBASE-KR MIF File
  • Design Example
  • SDC Timing Constraints
  • Acronyms
• 5. 1G/10 Gbps Ethernet PHY IP Core
  • 1G/10GbE PHY Release Information
  • Device Family Support
  • 1G/10 GbE PHY Performance and Resource Utilization
  • Parameterizing the 1G/10GbE PHY
  • 1GbE Parameters
  • Speed Detection Parameters
  • PHY Analog Parameters
  • 1G/10GbE PHY Interfaces
  • 1G/10GbE PHY Clock and Reset Interfaces
  • 1G/10GbE PHY Data Interfaces
  • XGMII Mapping to Standard SDR XGMII Data
  • Serial Data Interface
  • 1G/10GbE Control and Status Interfaces
  • Register Interface Signals
  • 1G/10GbE PHY Register Definitions
  • PMA Registers
  • PCS Registers
  • 1G/10 GbE GMII PCS Registers
  • PMA Registers
  • 1G/10GbE Dynamic Reconfiguration from 1G to 10GbE
  • 1G/10GbE PHY Arbitration Logic Requirements
  • 1G/10GbE PHY State Machine Logic Requirements
  • Editing a 1G/10GbE MIF File
  • Creating a 1G/10GbE Design
  • Dynamic Reconfiguration Interface Signals
  • 1G/10 Gbps Ethernet PHY IP Core
  • Design Example
  • Simulation Support
  • TimeQuest Timing Constraints
  • Acronyms
• 6. XAUI PHY IP Core
  • XAUI PHY Release Information
  • XAUI PHY Device Family Support
  • XAUI PHY Performance and Resource Utilization for Stratix IV Devices
  • XAUI PHY Performance and Resource Utilization for Arria V GZ and Stratix V Devices
  • Parameterizing the XAUI PHY
  • XAUI PHY General Parameters
  • XAUI PHY Analog Parameters
  • XAUI PHY Analog Parameters for Arria II GX, Cyclone IV GX, HardCopy IV and Stratix IV Devices
  • Advanced Options Parameters
  • XAUI PHY Configurations
  • XAUI PHY Ports
  • XAUI PHY Data Interfaces
    • SDR XGMII TX Interface
    • SDR XGMII RX Interface
    • Transceiver Serial Data Interface
  • XAUI PHY Clocks, Reset, and Powerdown Interfaces
  • XAUI PHY PMA Channel Controller Interface
  • XAUI PHY Optional PMA Control and Status Interface
  • XAUI PHY Register Interface and Register Descriptions
  • XAUI PHY Dynamic Reconfiguration for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX
  • XAUI PHY Dynamic Reconfiguration for Arria V, Arria V GZ, Cyclone V and Stratix V Devices
    • Logical Lane Assignment Restriction
    • XAUI PHY Dynamic Reconfiguration Interface Signals
  • SDC Timing Constraints
  • Simulation Files and Example Testbench
• 7. Interlaken PHY IP Core
  • Interlaken PHY Device Family Support
  • Parameterizing the Interlaken PHY
  • Interlaken PHY General Parameters
  • Interlaken PHY Optional Port Parameters
  • Interlaken PHY Analog Parameters
  • Interlaken PHY Interfaces
  • Interlaken PHY Avalon-ST TX Interface
  • Interlaken PHY Avalon-ST RX Interface
  • Interlaken PHY TX and RX Serial Interface
  • Interlaken PHY PLL Interface
  • Interlaken Optional Clocks for Deskew
  • Interlaken PHY Register Interface and Register Descriptions
  • Why Transceiver Dynamic Reconfiguration
  • Dynamic Transceiver Reconfiguration Interface
  • Interlaken PHY TimeQuest Timing Constraints
  • Interlaken PHY Simulation Files and Example Testbench
• 8. PHY IP Core for PCI Express (PIPE)
  • PHY for PCIe (PIPE) Device Family Support
  • PHY for PCIe (PIPE) Resource Utilization
  • Parameterizing the PHY IP Core for PCI Express (PIPE)
  • PHY for PCIe (PIPE) General Options Parameters
  • PHY for PCIe (PIPE) Interfaces
  • PHY for PCIe (PIPE) Input Data from the PHY MAC
  • PHY for PCIe (PIPE) Output Data to the PHY MAC
  • PHY for PCIe (PIPE) Clocks
  • PHY for PCIe (PIPE) Clock SDC Timing Constraints for Gen3 Designs
  • PHY for PCIe (PIPE) Optional Status Interface
  • PHY for PCIe (PIPE) Serial Data Interface
  • PHY for PCIe (PIPE) Register Interface and Register Descriptions
  • PHY for PCIe (PIPE) Link Equalization for Gen3 Data Rate
    • Phase 0
    • Phase 1
    • Phase 2 (Optional)
    • Phase 3 (Optional)
    • Recommendations for Tuning Link Partner’s Transmitter
  • Enabling Dynamic PMA Tuning for PCIe Gen3
  • PHY for PCIe (PIPE) Dynamic Reconfiguration
    • Logical Lane Assignment Restriction
  • PHY for PCIe (PIPE) Simulation Files and Example Testbench
• 9. Custom PHY IP Core
  • Device Family Support
  • Performance and Resource Utilization
  • Parameterizing the Custom PHY
    • General Options Parameters
    • Word Alignment Parameters
    • Rate Match FIFO Parameters
    • 8B/10B Encoder and Decoder Parameters
    • Byte Order Parameters
    • PLL Reconfiguration Parameters
    • Analog Parameters
    • Presets for Ethernet
  • Interfaces
    • Data Interfaces
    • Clock Interface
    • Optional Status Interface
    • Optional Reset Control and Status Interface
    • Register Interface and Register Descriptions
    • Custom PHY IP Core Registers
      • PMA Common Control and Status Registers
      • Reset Control Registers–Automatic Reset Controller
      • Reset Controls –Manual Mode
      • PMA Control and Status Registers
      • Custom PCS
    • SDC Timing Constraints
    • Dynamic Reconfiguration
• 10. Low Latency PHY IP Core
  • Device Family Support
  • Performance and Resource Utilization
  • Parameterizing the Low Latency PHY
  • General Options Parameters
  • Additional Options Parameters
  • PLL Reconfiguration Parameters
  • Low Latency PHY Analog Parameters
  • Low Latency PHY Interfaces
  • Low Latency PHY Data Interfaces
  • Optional Status Interface
  • Low Latency PHY Clock Interface
  • Optional Reset Control and Status Interface
  • Register Interface and Register Descriptions
  • Dynamic Reconfiguration
  • SDC Timing Constraints
  • Simulation Files and Example Testbench
• 11. Deterministic Latency PHY IP Core
  • Deterministic Latency Auto-Negotiation
  • Achieving Deterministic Latency
  • Deterministic Latency PHY Delay Estimation Logic
  • Deterministic Latency PHY Device Family Support
  • Parameterizing the Deterministic Latency PHY
    • General Options Parameters for Deterministic Latency PHY
    • Additional Options Parameters for Deterministic Latency PHY
    • PLL Reconfiguration Parameters for Deterministic Latency PHY
    • Deterministic Latency PHY Analog Parameters
  • Interfaces for Deterministic Latency PHY
  • Data Interfaces for Deterministic Latency PHY
  • Clock Interface for Deterministic Latency PHY
  • Optional TX and RX Status Interface for Deterministic Latency PHY
  • Optional Reset Control and Status Interfaces for Deterministic Latency PHY
  • Register Interface and Descriptions for Deterministic Latency PHY
  • Dynamic Reconfiguration for Deterministic Latency PHY
  • Channel Placement and Utilization for Deterministic Latency PHY
  • SDC Timing Constraints
  • Simulation Files and Example Testbench for Deterministic Latency PHY
• 12. Stratix V Transceiver Native PHY IP Core
  • Device Family Support for Stratix V Native PHY
  • Performance and Resource Utilization for Stratix V Native PHY
  • Parameter Presets
  • Parameterizing the Stratix V Native PHY
    • General Parameters for Stratix V Native PHY
    • PMA Parameters for Stratix V Native PHY
    • Standard PCS Parameters for the Native PHY
      • Standard PCS Pattern Generators
    • 10G PCS Parameters for Stratix V Native PHY
      • 10G PCS Pattern Generators
  • Interfaces for Stratix V Native PHY
    • Common Interface Ports for Stratix V Native PHY
    • Standard PCS Interface Ports
    • 10G PCS Interface
  • ×6/×N Bonded Clocking
  • xN Non-Bonded Clocking
  • SDC Timing Constraints of Stratix V Native PHY
  • Dynamic Reconfiguration for Stratix V Native PHY
  • Simulation Support
  • Slew Rate Settings
• 13. Arria V Transceiver Native PHY IP Core
  • Device Family Support
  • Performance and Resource Utilization
  • Parameterizing the Arria V Native PHY
  • General Parameters
  • PMA Parameters
    • TX PMA Parameters
    • TX PLL Parameters
    • RX PMA Parameters
  • Standard PCS Parameters
    • Phase Compensation FIFO
    • Byte Ordering Block Parameters
    • Byte Serializer and Deserializer
    • 8B/10B
    • Rate Match FIFO
    • Word Aligner and BitSlip Parameters
    • Bit Reversal and Polarity Inversion
  • Interfaces
    • Common Interface Ports
    • Standard PCS Interface Ports
  • SDC Timing Constraints
  • Dynamic Reconfiguration
  • Simulation Support
• 14. Arria V GZ Transceiver Native PHY IP Core
  • Device Family Support for Arria V GZ Native PHY
  • Performance and Resource Utilization for Arria V GZ Native PHY
  • Parameter Presets
  • Parameterizing the Arria V GZ Native PHY
    • General Parameters for Arria V GZ Native PHY
    • PMA Parameters for Arria V GZ Native PHY
    • Standard PCS Parameters for the Native PHY
      • Standard PCS Pattern Generators
    • 10G PCS Parameters for Arria V GZ Native PHY
      • 10G PCS Pattern Generators
  • Interfaces for Arria V GZ Native PHY
    • Common Interface Ports for Arria V GZ Native PHY
    • Standard PCS Interface Ports
    • 10G PCS Interface
  • SDC Timing Constraints of Arria V GZ Native PHY
  • Dynamic Reconfiguration for Arria V GZ Native PHY
  • Simulation Support
• 15. Cyclone V Transceiver Native PHY IP Core Overview
  • Cyclone Device Family Support
  • Cyclone V Native PHY Performance and Resource Utilization
  • Parameterizing the Cyclone V Native PHY
  • General Parameters
  • PMA Parameters
    • TX PMA Parameters
    • TX PLL Parameters
    • RX PMA Parameters
  • Standard PCS Parameters
    • Phase Compensation FIFO
    • Byte Ordering Block Parameters
    • Byte Serializer and Deserializer
    • 8B/10B
    • Rate Match FIFO
    • Word Aligner and BitSlip Parameters
    • Bit Reversal and Polarity Inversion
  • Interfaces
    • Common Interface Ports
    • Cyclone V Standard PCS Interface Ports
  • SDC Timing Constraints
  • Dynamic Reconfiguration
  • Simulation Support
• 16. Transceiver Reconfiguration Controller IP Core Overview
  • Transceiver Reconfiguration Controller System Overview
  • Transceiver Reconfiguration Controller Performance and Resource Utilization
  • Parameterizing the Transceiver Reconfiguration Controller IP Core
  • Parameterizing the Transceiver Reconfiguration Controller IP Core in Qsys
    • General Options Parameters
  • Transceiver Reconfiguration Controller Interfaces
    • MIF Reconfiguration Management Avalon-MM Master Interface
    • Transceiver Reconfiguration Interface
    • Reconfiguration Management Interface
  • Transceiver Reconfiguration Controller Memory Map
  • Transceiver Reconfiguration Controller Calibration Functions
    • Offset Cancellation
    • Duty Cycle Calibration
    • Auxiliary Transmit (ATX) PLL Calibration
  • Transceiver Reconfiguration Controller PMA Analog Control Registers
  • Transceiver Reconfiguration Controller EyeQ Registers
    • EyeQ Usage Example
  • Transceiver Reconfiguration Controller DFE Registers
  • Controlling DFE Using Register-Based Reconfiguration
    • Turning on DFE Continuous Adaptive mode
    • Turning on Triggered DFE Mode
    • Setting the First Tap Value Using DFE in Manual Mode
  • Transceiver Reconfiguration Controller AEQ Registers
  • Transceiver Reconfiguration Controller ATX PLL Calibration Registers
  • Transceiver Reconfiguration Controller PLL Reconfiguration
  • Transceiver Reconfiguration Controller PLL Reconfiguration Registers
  • Transceiver Reconfiguration Controller DCD Calibration Registers
  • Transceiver Reconfiguration Controller Channel and PLL Reconfiguration
    • Channel Reconfiguration
    • PLL Reconfiguration
  • Transceiver Reconfiguration Controller Streamer Module Registers
    • Mode 0 Streaming a MIF for Reconfiguration
    • Mode 1 Avalon-MM Direct Writes for Reconfiguration
  • MIF Generation
  • Creating MIFs for Designs that Include Bonded or GT Channels
  • MIF Format
  • xcvr_diffmifgen Utility
  • Reduced MIF Creation
  • Changing Transceiver Settings Using Register-Based Reconfiguration
    • Register-Based Write
    • Register-Based Read
  • Changing Transceiver Settings Using Streamer-Based Reconfiguration
    • Direct Write Reconfiguration
    • Streamer-Based Reconfiguration
  • Pattern Generators for the Stratix V and Arria V GZ Native PHYs
    • Enabling the Standard PCS PRBS Verifier Using Streamer-Based Reconfiguration
    • Enabling the Standard PCS PRBS Generator Using Streamer-Based Reconfiguration
    • Enabling the 10G PCS PRBS Generator or Verifier Using Streamer-Based Reconfiguration
    • Disabling the Standard PCS PRBS Generator and Verifier Using Streamer-Based Reconfiguration
  • Understanding Logical Channel Numbering
    • Two PHY IP Core Instances Each with Four Bonded Channels
    • One PHY IP Core Instance with Eight Bonded Channels
  • Two PHY IP Core Instances Each with Non-Bonded Channels
  • Transceiver Reconfiguration Controller to PHY IP Connectivity
  • Merging TX PLLs In Multiple Transceiver PHY Instances
  • Sharing Reconfiguration Interface for Multi-Channel Transceiver Designs
  • Loopback Modes
• 17. Transceiver PHY Reset Controller IP Core
  • Device Family Support for Transceiver PHY Reset Controller
  • Performance and Resource Utilization for Transceiver PHY Reset Controller
  • Parameterizing the Transceiver PHY Reset Controller IP
  • Transceiver PHY Reset Controller Parameters
  • Transceiver PHY Reset Controller Interfaces
  • Timing Constraints for Bonded PCS and PMA Channels
• 18. Transceiver PLL IP Core for Stratix V, Arria V, and Arria V GZ Devices
  • Parameterizing the Transceiver PLL PHY
  • Transceiver PLL Parameters
  • Transceiver PLL Signals
• 19. Analog Parameters Set Using QSF Assignments
  • Making QSF Assignments Using the Assignment Editor
  • Analog Settings for Arria V Devices
    • Analog Settings for Arria V Devices
      • XCVR_IO_PIN_TERMINATION
      • XCVR_REFCLK_PIN_TERMINATION
      • XCVR_TX_SLEW_RATE_CTRL
      • XCVR_VCCR_ VCCT_VOLTAGE
    • Analog Settings Having Global or Computed Values for Arria V Devices
      • CDR_BANDWIDTH_PRESET
      • PLL_BANDWIDTH_PRESET
      • XCVR_RX_DC_GAIN
      • XCVR_ANALOG_SETTINGS_PROTOCOL
      • XCVR_RX_COMMON_MODE_VOLTAGE
      • XCVR_RX_LINEAR_EQUALIZER_CONTROL
      • XCVR_RX_SD_ENABLE
      • XCVR_RX_SD_OFF
      • XCVR_RX_SD_ON
      • XCVR_RX_SD_THRESHOLD
      • XCVR_TX_COMMON_MODE_VOLTAGE
      • XCVR_TX_PRE_EMP_1ST_POST_TAP
      • XCVR_TX_RX_DET_ENABLE
      • XCVR_TX_RX_DET_MODE
      • XCVR_TX_VOD
      • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • Analog Settings for Arria V GZ Devices
    • Analog Settings for Arria V GZ Devices
      • XCVR_IO_PIN_TERMINATION
      • XCVR_REFCLK_PIN_TERMINATION
      • XCVR_RX_BYPASS_EQ_STAGES_234
      • XCVR_TX_SLEW_RATE_CTRL
      • XCVR_VCCA_VOLTAGE
      • XCVR_VCCR_VCCT_VOLTAGE
    • Analog Settings Having Global or Computed Default Values for Arria V GZ Devices
      • CDR_BANDWIDTH_PRESET
      • master_ch_number
      • PLL_BANDWIDTH_PRESET
      • reserved_channel
      • XCVR_ANALOG_SETTINGS_PROTOCOL
      • XCVR_RX_DC_GAIN
      • XCVR_RX_LINEAR_EQUALIZER_CONTROL
      • XCVR_RX_COMMON_MODE_VOLTAGE
      • XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
      • XCVR_RX_SD_ENABLE
      • XCVR_RX_SD_OFF
      • XCVR_RX_SD_ON
      • XCVR_RX_SD_THRESHOLD
      • XCVR_TX_COMMON_MODE_VOLTAGE
      • XCVR_TX_PRE_EMP_PRE_TAP_USER
      • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
      • XCVR_TX_PRE_EMP_1ST_POST_TAP
      • XCVR_TX_PRE_EMP_2ND_POST_TAP
      • XCVR_TX_PRE_EMP_INV_2ND_TAP
      • XCVR_TX_PRE_EMP_INV_PRE_TAP
      • XCVR_TX_PRE_EMP_PRE_TAP
      • XCVR_TX_RX_DET_ENABLE
      • XCVR_TX_RX_DET_MODE
      • XCVR_TX_RX_DET_OUTPUT_SEL
      • XCVR_TX_VOD
      • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • Analog Settings for Cyclone V Devices
    • XCVR_IO_PIN_TERMINATION
    • XCVR_REFCLK_PIN_TERMINATION
    • XCVR_TX_SLEW_RATE_CTRL
    • XCVR_VCCR_ VCCT_VOLTAGE
    • Analog Settings Having Global or Computed Values for Cyclone V Devices
      • CDR_BANDWIDTH_PRESET
      • PLL_BANDWIDTH_PRESET
      • XCVR_ANALOG_SETTINGS_PROTOCOL
      • XCVR_RX_DC_GAIN
      • XCVR_RX_LINEAR_EQUALIZER_CONTROL
      • XCVR_RX_COMMON_MODE_VOLTAGE
      • XCVR_RX_SD_ENABLE
      • XCVR_RX_SD_OFF
      • XCVR_RX_SD_ON
      • XCVR_RX_SD_THRESHOLD
      • XCVR_TX_COMMON_MODE_VOLTAGE
      • XCVR_TX_PRE_EMP_1ST_POST_TAP
      • XCVR_TX_RX_DET_ENABLE
      • XCVR_TX_RX_DET_MODE
      • XCVR_TX_VOD
      • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
  • Analog Settings for Stratix V Devices
    • Analog PCB Settings for Stratix V Devices
      • XCVR_GT_IO_PIN_TERMINATION
      • XCVR_IO_PIN_TERMINATION
      • XCVR_REFCLK_PIN_TERMINATION
      • XCVR_RX_BYPASS_EQ_STAGES_234
      • XCVR_TX_SLEW_RATE_CTRL
      • XCVR_VCCA_VOLTAGE
      • XCVR_VCCR_VCCT_VOLTAGE
    • Analog Settings Having Global or Computed Default Values for Stratix V Devices
      • CDR_BANDWIDTH_PRESET
      • master_ch_number
      • PLL_BANDWIDTH_PRESET
      • reserved_channel
      • XCVR_ANALOG_SETTINGS_PROTOCOL
      • XCVR_GT_RX_DC_GAIN
      • XCVR_RX_DC_GAIN
      • XCVR_RX_LINEAR_EQUALIZER_CONTROL
      • XCVR_GT_RX_COMMON_ MODE_VOLTAGE
      • XCVR_GT_RX_CTLE
      • XCVR_GT_TX_COMMON_ MODE_VOLTAGE
      • XCVR_GT_TX_PRE_EMP_1ST_POST_TAP
      • XCVR_GT_TX_PRE_EMP_ INV_PRE_TAP
      • XCVR_GT_TX_PRE_EMP_ PRE_TAP
      • XCVR_GT_TX_VOD_MAIN_TAP
      • XCVR_RX_COMMON_MODE_VOLTAGE
      • XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE
      • XCVR_RX_SD_ENABLE
      • XCVR_RX_SD_OFF
      • XCVR_RX_SD_ON
      • XCVR_RX_SD_THRESHOLD
      • XCVR_TX_COMMON_MODE_VOLTAGE
      • XCVR_TX_PRE_EMP_PRE_TAP_USER
      • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER
      • XCVR_TX_PRE_EMP_1ST_POST_TAP
      • XCVR_TX_PRE_EMP_2ND_POST_TAP
      • XCVR_TX_PRE_EMP_INV_2ND_TAP
      • XCVR_TX_PRE_EMP_INV_PRE_TAP
      • XCVR_TX_PRE_EMP_PRE_TAP
      • XCVR_TX_RX_DET_ENABLE
      • XCVR_TX_RX_DET_MODE
      • XCVR_TX_RX_DET_OUTPUT_SEL
      • XCVR_TX_VOD
      • XCVR_TX_VOD_PRE_EMP_CTRL_SRC
• 20. Migrating from Stratix IV to Stratix V Devices Overview
  • Differences in Dynamic Reconfiguration for Stratix IV and Stratix V Transceivers
  • Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices
  • Differences Between XAUI PHY Ports in Stratix IV and Stratix V Devices
  • Differences Between PHY IP Core for PCIe PHY (PIPE) Parameters in Stratix IV and Stratix V Devices
  • Differences Between PHY IP Core for PCIe PHY (PIPE) Ports for Stratix IV and Stratix V Devices
  • Differences Between Custom PHY Parameters for Stratix IV and Stratix V Devices
  • Differences Between Custom PHY Ports in Stratix IV and Stratix V Devices
• 21. Additional Information for the Transceiver PHY IP Core
  • Revision History for Previous Releases of the Transceiver PHY IP Core
  • How to Contact Altera