Verilink 2000 (34-00182) Product Manual - Manual (Page 47)

Maintenance Screen 4-13
NET PLB. The NET PLB loop (Figure 4-11) returns network RXD to TXD with
new framing, CRC, and FDL bits. Toward the DTE side, the CSU may be optioned
to send AIS on DTE TXD or LOOP back DTE RXD to TXD.
T1 Unloop
Pressing Enter takes down the specified loop from the currently selected element.
Far LLB
This field allows selecting how the in-band line loopback code is transmitted when
a far test is activated from the FAR/LOC front panel switch. Options are Framed
and Unframed per ANSI T1.403.
Setting this field does not activate the loop code transmission.
BERT Pattern
Specifies the pattern transmitted during a test. Modifying this field does not cause
the pattern to be transmitted (refer to Start Test). A BERT may also be activated
using the front panel switch. The CLEAR pattern passes the received data through
the unit (alarm detection and reporting is disabled while the test is active). The
choices are QRSS, 63, 511, 2047, 2
15
, 2
20
, 2
23
, 1:8, 3:24, ALT, and CLEAR.
Test Length
Defines the run time of test pattern generation and error accumulation. The
choices are Continuous, 15 min, 30 min, 60 min, and 24 Hour.
Start Test
Pressing Enter with the cursor on this field starts the selected test pattern. TEST IN
PROGRESS appears once the test has started. To end the test, press Enter on
STOP TEST.
Reset Errors
Pressing Enter with the cursor on this field clears the test error results.
The following fields are for display only. They reflect the selected test parameters
and the results of these tests only.
Framing, CRC, FDL
Tx
Rx
Rx
Tx
NET PLB, AIS to DTE
DTE
Interface
NET
Interface
AIS
Framing, CRC, FDL
Tx
Rx
Rx
Tx
NET PLB, LLB on DTE
DTE
Interface
NET
Interface
Figure 4-11 Network Payload Loopback