Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 123)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 123
April 2014
Chapter 9
VHDL Slave BFM
This section provides information about the VHDL slave BFM. It has an API that contains
procedures to configure the BFM and to access the dynamic
Transaction Record during the life
of the transaction.
Slave BFM Protocol Support
The AXI4-Stream slave BFM supports the full AMBA AXI4-Stream protocol.
Slave Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA
AXI4-Stream Protocol Specification chapter, which you can reference for details of the
following slave BFM API timing and events.
The AMBA AXI4-Stream Protocol Specification does not define any timescale or clock period
with signal events sampled and driven at rising ACLK edges. Therefore, the slave BFM does
not contain any timescale, timeunit, or timeprecision declarations. The signal setup and hold
times are specified in units of simulator time-steps.
Slave BFM Configuration
A slave BFM supports the full range of signals defined for the AMBA AXI4-Stream Protocol
Specification. It has parameters that you use to configure the widths of the data and ID signals,
and transaction fields to configure timeout factors, setup and hold times, and so on.
You can change the data and ID signals widths from their default setting by assigning them new
values, usually performed in the top-level module of the test bench. These new values are then
passed into the slave BFM using a parameter port list of the slave BFM module.
Table 9-1 lists the parameter names for the data and ID signals and their default values.
Table 9-1. Slave BFM Signal Width Parameters
Signal Width Parameter Description
AXI4_ID_WIDTH ID signal width in bits. This applies to the TID signal.
Refer to the AMBA AXI4-Stream Protocol Specification
for more details. Default: 18.