Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 76)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 76
VHDL API Overview
April 2014
Figure 7-1. VHDL BFM Internal Structure
Test Program VHDL
SystemVerilog BFM API
Configuration
Creating
Transaction
Waiting Events
Executing
Transaction
Access
Transaction
create*_transaction
1
set_config/get_config
execute_transaction/execute_transfer
2
wait_on
get_packet/get_transfer
get*/set*
3
Wire level
SystemVerilog Interface
Notes: 1. Refer to the create*_transaction()
2. Refer to the execute_transaction()
3. Refer to the get*()
Port map
SystemVerilog to VHDL
Rx_Transaction
queue queue
Tx_Transaction
Configuration
Maps API calls from VHDL to SystemVerilog
Translator Package
VHDL to SystemVerilog Wrapper