Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 212)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 212
SystemVerilog Master and Slave Test Programs
SystemVerilog Slave Test Program
April 2014
// This member controls the wait insertion in axi4 stream transfers
coming from master.
// Making ~m_insert_wait~ to 0 truns off the wait insertion.
bit m_insert_wait = 1;
// Task : ready_delay
// This is used to set ready delay to extend the transfer
task ready_delay();
// Making TREADY '0'. This will consume one cycle.
bfm.execute_stream_ready(0);
// Two clock cycle wait. In total 3 clock wait.
repeat(2) bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE);
// Making TREADY '1'.
bfm.execute_stream_ready(1);
endtask
///////////////////////////////////////////////////////////////////////
// Code user do not need to edit
///////////////////////////////////////////////////////////////////////
initial
begin
int i;
bit last;
axi4stream_transaction trans;
/*******************
** Initialisation **
*******************/
bfm.wait_on(AXI4STREAM_RESET_POSEDGE);
bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE);
// Packet receiving
forever
begin
trans = bfm.create_slave_transaction();
i = 0;
last = 0;
while(!last)
begin
if(m_insert_wait)
begin
ready_delay();
end
bfm.get_transfer(trans, i, last);
++i;
end
end
end
endmodule