Chapter 8 vhdl master bfm, Overloaded procedure common arguments, Master bfm protocol support – Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream User Manual

Page 87: Master timing and events, Vhdl master bfm, Api allows you to create a mast

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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3

87

April 2014

Chapter 8

VHDL Master BFM

This section provides information about the VHDL master BFM. It has an API that contains
procedures to configure the BFM and to access the dynamic

Transaction Record

during the life

of the transaction.

Overloaded Procedure Common Arguments

The BFMs use VHDL procedure overloading, which results in the prototype having a number
of definitions for each procedure. Their arguments are unique to each procedure and concern the
protocol or operational transaction fields for a transaction. These procedures have several
common arguments that may be optional and include the arguments described below:

transaction_id is an index number that identifies a specific transaction. Each new
transaction automatically increments the index number until reaching 255, the
maximum value, and then the index number automatically wraps to zero. The
transaction_id uniquely identifies each transaction when there are a number of
concurrently active transactions.

bfm_id is a unique identification number for each master, slave, and monitor BFM
within a multiple BFM test bench.

tr_if is a signal definition that passes the content of a transaction between the VHDL and
SystemVerilog environments.

Master BFM Protocol Support

The AXI4-Stream master BFM supports the full AMBA AXI4-Stream Protocol Specification.

Master Timing and Events

For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA
AXI4-Stream Protocol Specification chapter, which you can reference for details of the
following master BFM API timing and events.

The AMBA AXI4-Stream Protocol Specification does not define any timescale or clock period
with signal events sampled and driven at rising ACLK edges. Therefore, the master BFM does
not contain any timescale, timeunit, or timeprecision declarations. The signal setup and hold
times are specified in units of simulator time-steps.

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