Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 210)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 210
SystemVerilog Master and Slave Test Programs
SystemVerilog Master Test Program
April 2014
*******************/
bfm.wait_on(AXI4STREAM_RESET_POSEDGE);
bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE);
/************************
** Traffic generation: **
************************/
// 10 x packet with
// Number of transfer = i % 10. Values : 1, 2 .. 10
// id = i % 15. Values 0, 1, 2 .. 14
// dest = i %20. Values 0, 1, 2 .. 19
for(int i = 0; i < 10; ++i)
begin
transfer_count = (i % 10) + 1;
trans = bfm.create_master_transaction(transfer_count);
trans.id = i % 15;
trans.dest = i % 20;
for(int j = 0; j < (transfer_count * byte_count); ++j)
begin
trans.set_data(i + j, j);
if(((i + j)% 5) == 0)
begin
trans.set_byte_type(AXI4STREAM_NULL_BYTE, j);
end
else if(((i + j)% 5) == 1)
begin
trans.set_byte_type(AXI4STREAM_POS_BYTE, j);
end
else
begin
trans.set_byte_type(AXI4STREAM_DATA_BYTE, j);
end
end
bfm.execute_transaction(trans);
end
// 10 x packet at transfer level with
// Number of transfer = i % 10. Values : 1, 2 .. 10
// id = i % 15. Values 0, 1, 2 .. 14
// dest = i %20. Values 0, 1, 2 .. 19
for(int i = 0; i < 10; ++i)
begin
transfer_count = (i % 10) + 1;
trans = bfm.create_master_transaction(transfer_count);
trans.id = i % 15;
trans.dest = i % 20;
for(int j = 0; j < transfer_count; ++j)
begin
for(int k = 0; k < byte_count; ++k)
begin
trans.set_data(k+j, ((j*byte_count)+k));
if(((i + j)% 5) == 0)
begin
trans.set_byte_type(AXI4STREAM_NULL_BYTE, ((j*byte_count)+k));
end
else if(((i + j)% 5) == 1)
begin
trans.set_byte_type(AXI4STREAM_POS_BYTE, ((j*byte_count)+k));