M_insert_wait, Ready_delay(), Example 6-4. m_insert_wait – Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream User Manual
Page 72: Example 6-5. ready_delay()
Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
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SystemVerilog Tutorials
Verifying a Master DUT
April 2014
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to configure the delay of the TREADY signal.
m_insert_wait
The m_insert_wait configuration variable controls the insertion of a delay for the TREADY
signal defined by the
task. To insert a delay set m_insert_wait to 1 (default);
otherwise, set to 0, as shown in
Example 6-4. m_insert_wait
// This member controls the wait insertion in axi4 stream transfers
// coming from master.
// Assigning m_insert_wait to 0 turns off the wait insertion.
bit m_insert_wait = 1;
ready_delay()
The ready_delay task inserts a delay for the TREADY signal. The delay value extends the
length of a protocol transfer by a defined number of ACLK cycles. The starting point of the
delay is determined by the completion of a previous transfer, or from the first positive ACLK
edge after reset at the start of simulation.
The ready_delay() task initially sets TREADY to 0 by calling the
task,
. The delay is inserted by calling the
task within a repeat()
statement. You can edit the number of repetitions to change the delay. After the delay, the
task is called again to set the TREADY signal to 1.
Example 6-5. ready_delay()
// Task : ready_delay
// This is used to set ready delay to extend the transfer
task ready_delay();
// Making TREADY '0'. This will consume one cycle.
bfm.execute_stream_ready(0);
// Two clock cycle wait. In total 3 clock wait.
repeat(2) bfm.wait_on(AXI4STREAM_CLOCK_POSEDGE);
// Making TREADY '1'.
bfm.execute_stream_ready(1);
endtask
Note
In addition to the above tasks and variables, you can configure other aspects of the slave
BFM by using these functions: