Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 216)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 216
VHDL Master and Slave Test Programs
VHDL Slave BFM Code Example
April 2014
VHDL Slave BFM Code Example
The example code in this section is a simplified AXI4-Stream slave that illustrates how you can
use the mgc_axi4stream_master BFM.
--
*************************************************************************
****
--
-- Copyright 2007-2013 Mentor Graphics Corporation
-- All Rights Reserved.
--
-- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
THE PROPERTY OF
-- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE
TERMS.
--
--
*************************************************************************
****
--
-- This is a simple example of an AXI4STREAM Slave to demonstrate the
mgc_axi4stream_slave BFM usage.
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.all;
use work.mgc_axi4stream_bfm_pkg.all;
entity slave_test_program is
generic(
AXI4_ID_WIDTH : integer := 18;
AXI4_USER_WIDTH : integer := 8;
AXI4_DEST_WIDTH : integer := 18;
AXI4_DATA_WIDTH : integer := 1024;
index : integer range 0 to 511 := 0
);
end slave_test_program;
architecture slave_test_program_a of slave_test_program is
--This member controls the wait insertion in axi4 stream transfers
coming from master.
-- Making ~m_insert_wait~ to '0' truns off the wait insertion.
signal m_insert_wait : std_logic := '1';
procedure ready_delay(signal tr_if : inout axi4stream_vhd_if_struct_t);
--///////////////////////////////////////////////
-- Code user could edit according to requirements
--///////////////////////////////////////////////
-- Procedure : ready_delay
-- This is used to set ready delay to extend the transfer