Chapter 2 systemverilog api overview, Figure 2-1. systemverilog bfm internal structure – Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream User Manual
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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
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April 2014
Chapter 2
SystemVerilog API Overview
This section provides the functional description of the SystemVerilog (SV) API for all the BFM
(master, slave, and monitor) components. For each BFM, you can configure the protocol
transaction fields that are executed on the protocol signals, as well as control the operational
transaction fields that set delay and timeout values.
In addition, each BFM API has tasks that wait for certain events to occur on the system clock
and reset signals, and tasks to get and set information about a particular transaction.
Figure 2-1. SystemVerilog BFM Internal Structure
Test Program SystemVerilog
Notes: 1. Refer to
2. Refer to
3. Refer to
SystemVerilog BFM API
Configuration
Creating
Transaction
Waiting Events
Executing
Transaction
Access
Transaction
create_*_transaction
1
set_config/get_config
get_packet/get_transfer
wait_on
3
Rx_Transaction
queue
queue
Tx_Transaction
Configuration
Wire level
get*/set*
execute_transaction/execute_transfer
2
SystemVerilog interface