Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 186)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 186
VHDL Tutorials
Verifying a Master DUT
April 2014
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Configuration variable m_insert_wait to insert a delay in the assertion of the TREADY
protocol signal
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Procedure ready_delay() to configure the delay of the TREADY signal
m_insert_wait
The m_insert_wait configuration signal controls the insertion of a delay for the TREADY
protocol signal defined by the
ready_delay() procedure. To insert a delay, set m_insert_wait to 1
(default); otherwise, set to 0 as shown in Example 11-4 .
Example 11-4. m_insert_wait
-- This signal controls the wait insertion in axi4 stream transfers
-- coming from master.
-- Making ~m_insert_wait~ to '0' truns off the wait insertion.
signal m_insert_wait : std_logic := '1';
ready_delay()
The ready_delay procedure inserts a delay for the TRREADY signal. The delay value extends
the length of a protocol transfer by a defined number of ACLK cycles. The starting point of the
delay is determined by the completion of a previous transfer, or from the first positive ACLK
edge after reset at the start of simulation.
The ready_delay() task initially sets TREADY to 0 by calling the execute_stream_ready()
procedure, as shown in Example 11-5 . The delay is inserted by calling the wait_on() procedure
within a for loop statement. You can edit the number of repetitions to change the delay. After
the delay, the
execute_stream_ready() procedure is called again to set the TREADY signal to 1.
Example 11-5. ready_delay
procedure ready_delay(signal tr_if : inout axi4stream_vhd_if_struct_t);
--///////////////////////////////////////////////
-- Code user could edit according to requirements
--///////////////////////////////////////////////
-- Procedure : ready_delay
-- This is used to set ready delay to extend the transfer
procedure ready_delay(signal tr_if : inout axi4stream_vhd_if_struct_t) is
begin
-- Making TREADY '0'. This will consume one cycle.
execute_stream_ready(0, index, tr_if);
-- Two clock cycle wait. In total 3 clock wait.
for i in 0 to 1 loop
wait_on(AXI4STREAM_CLOCK_POSEDGE, index, tr_if);
end loop;
-- Making TREADY '1'.
execute_stream_ready(1, index, tr_if);
end ready_delay;