Altera Mentor Verification IP Altera Edition AMBA AXI4-Stream - Manual (Page 188)

Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3 188
VHDL Tutorials
Verifying a Master DUT
April 2014
Example 11-7. Transfer Receiving
loop
create_slave_transaction(trans, index, axi4stream_tr_if_0(index));
i := 0;
last := 0;
while(last = 0) loop
if(m_insert_wait = '1') then
-- READY is through path 0
ready_delay(axi4stream_tr_if_0(index));
end if;
get_transfer(trans, i, last, index, axi4stream_tr_if_0(index));
i := i + 1;
end loop;
end loop;
wait;
end process;