Renesas SH7781 - Manual (Page 1068)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1038 of 1658
REJ09B0261-0100
SPTRW
D3
D2
R
Q D
SCKIO
C
SPTRR
SPTRW
R
Q D
SCKDT
C
Clock output enable signal*
Serial clock output signal*
Serial clock input signal*
Serial input enable signal*
Peripheral bus
Reset
Reset
Legend:
SPTRW: Write to SCSPTR
SPTRR: Read from SCSPTR
Note: * The SCIFn_SCK pin function is designated as internal clock output or external clock input
by the C/
A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR.
SCIFn_SCK
Figure 21.4 SCIFn_SCK Pin (n
= 0 to 5)
SPTRW
D1
D0
R
Q D
SPB2IO
C
SPTRW
R
Q D
SPB2DT
C
Legend:
SPTRW: Write to SCSPTR
SCIFn_TXD
Transmit enable signal
Serial transmit data
Peripheral bus
Reset
Reset
Figure 21.5 SCIFn_TXD Pin (n
= 0 to 5)