Renesas SH7781 - Manual (Page 486)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 456 of 1658
REJ09B0261-0100
Table 11.22 Register Settings for Divided-Up
DACKn Output in DMA1 Transfer in Write
Access Using the MPX Interface
Not Divided Divided
Bus Width
[Bit] Access
Size
Bus Cycle
Number IWW
in CSnBCR
IW1 and IW0 in
CSnWCR IWW
in CSnBCR
Byte 1
⎯ ⎯ Undividable
Word 1
⎯ ⎯ Undividable
Longword 1
⎯ ⎯ Undividable
16 bytes 4 B'000 B'11 to B'01 B'111 to B'001
32
32 bytes 1
⎯ ⎯ Undividable
64 Byte 1
⎯ ⎯ Undividable
Word 1
⎯ ⎯ Undividable
Longword 1
⎯ ⎯ Undividable
16 bytes 4 B'000 B'11 to B'01 B'111 to B'001
32 bytes 1
⎯ ⎯ Undividable
Note: "
⎯" means an arbitrary setting value. When transfer is done in a single bus cycle, DACKn
is not divided up because
DACKn is output once in DMA1 transfer.