Renesas SH7781 - Manual (Page 1632)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1602 of 1658
REJ09B0261-0100
32.3.8 TMU Module Signal Timing
Table 32.13 TMU Module Signal Timing
Conditions: V
DDQ
= 3.0 to 3.6 V, V
DD
= 1.1 V, T
a
=
−40 to 85°C, C
L
= 30 pF, PLL2 on
Module Item Symbol Min. Max. Unit Figure Remarks
TMU Timer clock pulse width
(high) t
TCLKWH
4 — t
Pcyc
32.41
Timer clock pulse width
(low) t
TCLKWL
4 —
Timer clock rise time t
TCLKr
— 0.8
Timer clock fall time t
TCLKf
— 0.8
Note: t
Pcyc
is the period of one peripheral clock (Pck) cycle.
t
TCLKWH
t
TCLKWL
t
TCLKf
t
TCLKr
TCLK
Figure 32.41 TCLK Input Timing