4 watchdog timer counter (wdtcnt) – Renesas SH7781 User Manual
Page 797
16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 767 of 1658
REJ09B0261-0100
16.3.4
Watchdog Timer Counter (WDTCNT)
WDTCNT is a 32-bit read-only register comprising a 12-bit counter that is incremented by the
WDTBCNT overflow signal. When WDTCNT overflows, a reset of the selected type is initiated
in watchdog timer mode, or an interrupt is generated in interval timer mode.
WDTCNT is only reset by a power-on reset. Writing to this register is invalid.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
WDTCNT
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
31 to 12
⎯ All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0
WDTCNT
All 0
R
Counter value