Renesas SH7781 - Manual (Page 727)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 697 of 1658
REJ09B0261-0100
• DMARS3
Bit Bit Name
Initial
Value R/W Descriptions
15
14
13
12
11
10
C7MID5
C7MID4
C7MID3
C7MID2
C7MID1
C7MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 7 (MID)
See table 14.3.
9
8
C7RID1
C7RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 7 (RID)
See table 14.3.
7
6
5
4
3
2
C6MID5
C6MID4
C6MID3
C6MID2
C6MID1
C6MID0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Transfer request source module ID5 to ID0 for DMA
channel 6 (MID)
See table 14.3.
1
0
C6RID1
C6RID0
0
0
R/W
R/W
Transfer request source register ID1 and ID0 for DMA
channel 6 (RID)
See table 14.3.