35 port j pull-up control register (pjpupr) – Renesas SH7781 User Manual
Page 1466
28. General Purpose I/O Ports (GPIO)
Rev.1.00 Jan. 10, 2008 Page 1436 of 1658
REJ09B0261-0100
28.2.35
Port J Pull-Up Control Register (PJPUPR)
PJPUPR is an 8-bit readable/writable register that performs the pull-up control for each of the port
J7 to J0 (PJ7 to PJ0) pins when the port J pins are used by peripheral modules. When the port J
pins are used by the GPIO, the setting for this register is ignored.
0
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1
PJ0
PUPR
PJ1
PUPR
PJ2
PUPR
PJ3
PUPR
PJ4
PUPR
PJ5
PUPR
PJ6
PUPR
PJ7
PUPR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
Bit Bit
Name
Initial
value R/W Description
7 PJ7PUPR
1 R/W
6 PJ6PUPR
1 R/W
5 PJ5PUPR
1 R/W
4 PJ4PUPR
1 R/W
3 PJ3PUPR
1 R/W
2 PJ2PUPR
1 R/W
1 PJ1PUPR
1 R/W
Pull-up of each Port J pin can be controlled
independently.
0: PJn pull-up off
1: PJn pull-up on
0 PJ0PUPR
1 R/W
Note: n = 7 to 0