Renesas SH7781 - Manual (Page 753)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 723 of 1658
REJ09B0261-0100
CLKOUT
Bus cycle
DREQ
(Overrun 0, High level)
DRAK
(High-active)
DACK
(High-active)
CLKOUT
Bus cycle
DREQ
(Overrun 1, High level)
DRAK
(High-active)
DACK
(High-active)
CPU DMAC CPU
1st acceptance
Acceptance started
Accepted after one cycle of CLKOUT
at the falling edge of DACK
: Non-sensitive period
1st acceptance
Acceptance started
Accepted after one cycle of CLKOUT
at the rising edge of DACK
CPU DMAC CPU
2nd acceptance
2nd acceptance
Figure 14.16 Example 1 of DREQ Input Detection in Cycle Steal Mode Level Detection
(Byte Transfer in 8/16/32/64-Bit Bus Width, Word Transfer in 16/32/64-Bit Bus Width, or
Longword Transfer in 32/64-Bit Bus Width)